ADS5271 datasheet(8/42 Pages) TI2

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ADS5287

SBAS428D – JANUARY 2008 – REVISED JUNE 2012

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Table 2. PIN DESCRIPTIONS: QFN-64 (continued)

PIN NAME

DESCRIPTION

PIN NUMBER

# OF PINS

IN5N

Negative differential input signal, channel 5

IN5P

Positive differential input signal, channel 5

IN6N

Negative differential input signal, channel 6

IN6P

Positive differential input signal, channel 6

IN7N

Negative differential input signal, channel 7

IN7P

Positive differential input signal, channel 7

IN8N

Negative differential input signal, channel 8

IN8P

Positive differential input signal, channel 8

INT/EXT

Internal/external reference mode select input

ISET

Bias pin—56.2k

Ω to ground

LCLKN

LVDS bit clock (6X)—negative output

LCLKP

LVDS bit clock (6X)—positive output

LVDD

Digital and I/O power supply, 1.8V

LVSS

Digital ground

12, 14, 36

OUT1N

LVDS channel 1—negative output

OUT1P

LVDS channel 1—positive output

OUT2N

LVDS channel 2—negative output

OUT2P

LVDS channel 2—positive output

OUT3N

LVDS channel 3—negative output

OUT3P

LVDS channel 3—positive output

OUT4N

LVDS channel 4—negative output

OUT4P

LVDS channel 4—positive output

OUT5N

LVDS channel 5—negative output

OUT5P

LVDS channel 5—positive output

OUT6N

LVDS channel 6—negative output

OUT6P

LVDS channel 6—positive output

OUT7N

LVDS channel 7—negative output

OUT7P

LVDS channel 7—positive output

OUT8N

LVDS channel 8—negative output

OUT8P

LVDS channel 8—positive output

Power-down input

REFB

Negative reference input/output

REFT

Positive reference input/output

RESET

Active low RESET input

SCLK

Serial clock input

SDATA

Serial data input

Test pin, do not use

VCM

Common-mode output pin, 1.5V output

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