ADS5271 datasheet(35/42 Pages) TI2

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Threshold 1

Threshold 2

Threshold 3

10 MHz

45 MHz

65 MHz

Sampling Frequency

ADS5287

www.ti.com

SBAS428D – JANUARY 2008 – REVISED JUNE 2012

PLL OPERATION ACROSS SAMPLING

Step 2: Disable the PLL automatic switch and set

FREQUENCY

the PLL configuration depending on the clock

frequency

The ADS528X uses a PLL for generating the high

speed bit clock (LCLK), the frame clock (ADCLK) &

SAMPLE CLOCK FREQUENCY

internal clocks for the serializer operation.

RANGE (MSPS)

Min

Max

Address

Data

To enable operation across the entire frequency

range, the PLL is automatically configured to one of

0060

four

states,

depending

the

sampling

clock

00A0

frequency range. The frequency range detection is

automatic and each time the sampling frequency

With the above settings applied for the respective

crosses

threshold,

the

PLL

changes

its

frequency ranges, the part will continue to

configuration to a new state. To prevent unwanted

operate as per the stated datasheet specifications

toggling of PLL state around a threshold, the circuit

for

all

timing

parameters

all

specified

has an inbuilt hysteresis. The ADS528x has three

frequencies, EXCEPT for the timing specifications

thresholds – taking into account the hysteresis range

at 40MSPS. At 40MSPS, the affected parameters

of each threshold, variation across devices and

are – Data setup time, Data hold time and Clock

temperature, the thresholds can span the sampling

propagation delay (refer to LVDS Timing ).

clock frequency range from 10MHz to 45MHz.

2. For sampling clock frequency

≥ 45MSPS

As there are no PLL thresholds beyond 45MHz,

no change in PLL configuration can occur as the

temperature

the

system

stabilizes.

The

ADS528x can be used in the system without

using the above software fix.

INPUT OVER-VOLTAGE RECOVERY

The

differential

peak-to-peak

full-scale

range

supported by the ADS5287 is nominally 2.0V. The

ADS5287 is specially designed to handle an over-

Figure 39. Variation of Thresholds Across

voltage condition where the differential peak-to-peak

Sampling Frequency

voltage can be up to twice the ADC full-scale range.

If the input common-mode is not considerably off

from VCM during overload (less than 300mV around

Based on actual system clock frequency, there are

the nominal value of 1.5V), recovery from an over-

two scenarios:

voltage pulse input of twice the amplitude of a full-

1. For sampling clock frequency < 45MSPS

scale pulse is expected to be within one clock cycle

After

system

power

up,

depending

the

when the input switches from overload to zero signal.

frequency

operation

and

the

frequency

threshold for the given device, the frequency

REFERENCE CIRCUIT

range detection circuit may change state once. In

The digital beam-forming algorithm in an ultrasound

some applications where a timing calibration

system relies on gain matching across all receiver

might be done at the system level once after

channels. A typical system would have about 12 octal

power up, this subsequent change of the PLL

ADCs on the board. In such a case, it is critical to

state might be undesirable as it can cause a loss

ensure that the gain is matched, essentially requiring

of alignment in the received data. A software fix

the reference voltages seen by all the ADCs to be the

for eliminating this one-time change of PLL state

same. Matching references within the eight channels

exists using the serial register interface:

of a chip is done by using a single internal reference

–

Disable the automatic switch of the PLL

voltage buffer. Trimming the reference voltages on

configuration based on frequency detected.

each

chip

during

production

ensures

that

the

–

In addition to disabling the switching, it is also

reference voltages are well-matched across different

required to set the PLL to the correct

chips.

configuration, depending on the sample clock

frequency used in the system.

All bias currents required for the internal operation of

the device are set using an external resistor to

The following sequence of register writes must be

ground at the ISET pin. Using a 56.2kΩ resistor on ISET

followed:

generates an internal reference current of 20

μA. This

Step 1: Write Address = 0x01, Data = 0x0010

current is mirrored internally to generate the bias

current for the internal blocks. Using a larger external

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