WM8994ECSSLASHR datasheet(188/363 Pages) CIRRUS

188 / 363 page

WM8994

188

Rev 4.6

AUDIO INTERFACE AIF3 CONFIGURATION

The WM8994 provides two full audio interfaces, AIF1 and AIF2. A third interface, AIF3, is partially

supported, using multiplexers to re-configure alternate connections to AIF1 or AIF2. The relevant

multiplexers are illustrated in Figure 66.

Note that, in addition to providing alternate input / output pins to the audio interfaces AIF1 and AIF2,

the multiplexers also provide the capability to link AIF3 pins directly to AIF2 pins, without involving the

AIF2 interface processing resource.

All of the AIF3 connections are supported on pins which also provide GPIO functions. These pins

must be configured as AIF functions when used as audio interface pins. See “General Purpose

Input/Output

”.

DIGITAL AUDIO

INTERFACE 2 (AIF2)

DIGITAL AUDIO

INTERFACE 1 (AIF1)

AIF1_DACDAT_SRC

AIF3_ADCDAT_SRC[1:0]

AIF2_DACDAT_SRC

AIF2_ADCDAT_SRC

Figure 66 Audio Interface AIF3 Configuration

The GPIO8 pin also supports the DACDAT3 function. When configured as DACDAT3, this pin may be

used as an alternate data input pin to AIF1 or AIF2. The data input source for AIF1 is selected using

the AIF1_DACDAT_SRC register. The data input source for AIF2 is selected using the

AIF2_DACDAT_SRC register.

The GPIO8 pin is configured as DACDAT3 by setting GP8_FN = 00h. Note that it is also necessary to

set GP3_FN = 00h and GP5_FN = 00h when using the DACDAT3 function on the GPIO8 pin.

The GPIO9 pin also supports the ADCDAT3 function. When configured as ADCDAT3, this pin may be

used as an alternate data output pin to AIF1 or AIF2. It is also possible to route the DACDAT2 input

pin to the ADCDAT3 output. The ADCDAT3 source is selected using the AIF3_ADCDAT_SRC

The DACDAT3 input pin referenced above may also be routed to the ADCDAT2 output. The

ADCDAT2 source is selected using the AIF2_ADCDAT_SRC register.

The GPIO10 pin also supports the LRCLK3 function. When configured as LRCLK3, this pin outputs

the DACLRCLK signal from AIF1 or AIF2. The applicable AIF source is determined automatically as

defined in Table 102. Note that the LRCLK3 signal is also controlled by the logic illustrated in Figure

62 (AIF1) or Figure 65 (AIF2), depending on the selected AIF source.

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