WM8994ECSSLASHR datasheet(191/363 Pages) CIRRUS

191 / 363 page

WM8994

Rev 4.6

191

CLOCKING AND SAMPLE RATES

The WM8994 requires a clock for each of the Digital Audio Interfaces (AIF1 and AIF2). These may be

derived from a common clock reference, or from independent references. Under typical clocking

configurations, many commonly-used audio sample rates can be derived directly from the external

reference; for additional flexibility, the WM8994 incorporates two Frequency Locked Loop (FLL)

circuits to perform frequency conversion and filtering.

External clock signals may be connected via MCLK1 and MCLK2. (Note that MCLK2 is an alternate

function of the GPIO2 pin.) In AIF Slave modes, the BCLK or LRCLK signals may be used as a

reference for the AIF clocks.

The WM8994 performs stereo full-duplex sample rate conversion between the audio interfaces AIF1

and AIF2, enabling digital audio to be routed between the interfaces, and asynchronous audio data to

be mixed together.

See “Sample Rate Conversion” for further details.

In AIF Slave modes, it is important to ensure the applicable AIF clock (AIF1CLK or AIF2CLK) is

synchronised with the associated external LRCLK. This can be achieved by selecting an MCLK input

that is derived from the same reference as the LRCLK, or can be achieved by selecting the external

BCLK or LRCLK signals as a reference input to one of the FLLs, as a source for the AIF clock.

If the AIF clock is not synchronised with the LRCLK, then clicks arising from dropped or repeated

audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks.

See “Applications Information” for further details on valid clocking configurations.

Clocking for the Audio Interfaces is provided by AIF1CLK and AIF2CLK for AIF1 and AIF2

respectively. An additional internal clock, SYSCLK is derived from either AIF1CLK or AIF2CLK in

order to support the DSP core functions, Charge Pump, Class D switching amplifier, DC servo control,

Control Write Sequencer and other internal functions.

The following operating limits must be observed when configuring the WM8994 clocks. Failure to

observe these limits will result in degraded performance and/or incorrect system functionality. Latency

in the WM8994 signal paths is reduced at high SYSCLK frequencies; power consumption is reduced

at low SYSCLK frequencies.



SYSCLK

 12.5MHz



SYSCLK

 4.096MHz



SYSCLK

 256 x fs (where fs = fastest audio sample rate in use)



AIF1CLK

 12.5MHz



AIF1CLK

 256 x AIF1 sample rate (AIF1_SR)



AIF2CLK

 12.5MHz



AIF2CLK

 256 x AIF2 sample rate (AIF2_SR)

Note that, if DAC_OSR128 = 0 and ADC_OSR128 = 0, then a slower SYSCLK frequency is possible;

in this case, the requirement is SYSCLK

 2.048MHz.

Note that, under specific operating conditions, clocking ratios of 128 x fs and 192 x fs are possible;

this is described in the “Digital to Analogue Converter (DAC)” section.

The SYSCLK frequency must be

 256 x fs, (where fs is the faster rate of AIF1_SR or AIF2_SR). The

SYSCLK frequency is derived from AIF1CLK or AIF2CLK, as selected by the SYSCLK_SRC register

(see Table 109).

Note that the bandwidth of the digital audio mixing paths will be determined by the sample rate of

whichever AIF is selected as the SYSCLK source. When using only one audio interface, the active

interface should be selected as the SYSCLK source. For best audio performance when using AIF1

and AIF2 simultaneously, the SYSCLK source must select the AIF with the highest sample rate

(AIFn_SR).

WM8994ECS/R 数据表(PDF) 191 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 191 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

WM8994ECS/R 数据表(PDF) 191 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 191 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载