WM8994ECSSLASHR datasheet(195/363 Pages) CIRRUS

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WM8994

Rev 4.6

195

AIF2CLK ENABLE

The AIF2CLK_SRC register is used to select the AIF2CLK source. The source may be MCLK1,

MCLK2, FLL1 or FLL2. If either of the Frequency Locked Loops is selected as the source, then the

FLL(s) must be enabled and configured as described later.

The AIF2CLK clock may be adjusted by the AIF2CLK_DIV divider, which provides a divide-by-two

option. The selected source may also be inverted by setting the AIF2CLK_INV bit.

The maximum AIF2CLK frequency is specified in the “Electrical Characteristics” section. Note that,

when AIF2CLK_DIV = 1, the maximum frequency limit applies to the divided-down AIF2CLK

frequency.

The AIF2CLK is enabled by the register bit AIF2CLK_ENA. This bit should be set to 0 when

reconfiguring the clock sources. It is not recommended to change AIF2CLK_SRC while the

AIF2CLK_ENA bit is set.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R516 (0204h)

AIF 2

Clocking (1)

4:3

AIF2CLK_SR

AIF2CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

AIF2CLK_INV

AIF2CLK Invert

0 = AIF2CLK not inverted

1 = AIF2CLK inverted

AIF2CLK_DIV

AIF2CLK Divider

0 = AIF2CLK

1 = AIF2CLK / 2

AIF2CLK_EN

AIF2CLK Enable

0 = Disabled

1 = Enabled

Table 107 AIF2CLK Enable

AIF2 CLOCKING CONFIGURATION

The WM8994 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The AIF2

clocking configuration is selected using 4 control fields, which are set according to the required AIF

digital audio sample rate, and the ADC/DAC clocking rate.

The AIF2_SR register is set according to the AIF2 sample rate. Note that 88.2kHz and 96kHz modes

are supported for AIF2 input (DAC playback) only.

The AIF2CLK_RATE register is set according to the ratio of AIF2CLK to the AIF2 sample rate. Note

that there a some restrictions on the supported clocking ratios, depending on the selected sample rate

and operating conditions. The supported configurations are detailed in the “Digital Microphone

Interface

”, “Analogue to Digital Converter (ADC)” and “Digital to Analogue Converter (DAC)” sections,

according to each applicable function.

The audio interface can support different sample rates for the input data (DAC path) and output data

(ADC path) simultaneously. In this case, the AIF2_SR and AIF2CLK_RATE fields should be set

according to the faster of the two sample rates.

When different sample rates are used for input data (DAC path) and output data (ADC path), the

clocking of the slower path is set using AIF2DAC_DIV (if the AIF input path has the slower sample

rate) or AIF2ADC_DIV (if the AIF output path has the slower sample rate). The appropriate divider is

set according to the ratio of the two sample rates.

For example, if AIF2 input uses 48kHz sample rate, and AIF2 output uses 8kHz, then AIF2ADC_DIV

should be set to 110b (divide by 6).

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