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WM8994ECS/R 数据表(PDF) 198 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 198 Page - Cirrus Logic |
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198 / 363 page  WM8994 198 Rev 4.6 The WM8994 generates a 256kHz clock for internal functions; TOCLK and DBCLK are derived from this 256kHz clock. In order to generate this clock correctly when SYSCLK_SRC = 0, valid settings are required for AIF1_SR and AIF1CLK_RATE. To generate this clock correctly when SYSCLK_SRC = 1, valid settings are required for AIF2_SR and AIF2CLK_RATE. The WM8994 Clocking is illustrated in Figure 68. SYSCLK Clocking for Digital Mixer Processing SYSDSPCLK_ENA Clocking for PGA Zero-Cross timeouts f/N f/N f/N 256kHz AIFn_SR [3:0] AIFnCLK_RATE [3:0] (Either AIF1 or AIF2 settings selected, depending on SYSCLK_SRC.) TOCLK_DIV [2:0] DBCLK_DIV [2:0] TOCLK_ENA f/N OPCLK OPCLK may be output on a GPIO pin OPCLK_DIV [2:0] OPCLK_ENA Charge Pump clock f/N (configured automatically) CP_ENA Class D output driver clock f/N SPKOUTR_ENA or SPKOUTL_ENA AIFn_SR [3:0] AIFnCLK_RATE [3:0] (Either AIF1 or AIF2 settings selected, depending on SYSCLK_SRC.) f/N AIFn_SR [3:0] AIFnCLK_RATE [3:0] (Either AIF1 or AIF2 settings selected, depending on SYSCLK_SRC.) Clocking for ADC, DAC and Digital Microphone (DMICCLK) AIF2_SR [3:0] AIF2CLK_RATE [3:0] AIF2DSPCLK_ENA AIF1_SR [3:0] AIF1CLK_RATE [3:0] AIF1DSPCLK_ENA AIF2 DSP AIF1 DSP Clocking for AIF1 DSP functions Clocking for AIF2 DSP functions Clocking for GPIO de-bounce Figure 68 System Clocking |
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