WM8994ECSSLASHR datasheet(202/363 Pages) CIRRUS

202 / 363 page

WM8994

202

Rev 4.6

The FLL is enabled using the FLLn_ENA register bit (where n = 1 for FLL1 and n = 2 for FLL2). Note

that the other FLL registers should be configured before enabling the FLL; the FLLn_ENA register bit

should be set as the final step of the FLLn enable sequence.

When changing FLL settings, it is recommended that the digital circuit be disabled via FLLn_ENA and

then re-enabled after the other register settings have been updated. When changing the input

reference frequency FREF, it is recommended that the FLL be reset by setting FLLn_ENA to 0.

Note that, for normal operation of the FLLs, the reference voltage VMID and the bias current must

also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls

VMID_SEL and BIAS_ENA.

The field FLLn_REFCLK_DIV provides the option to divide the input reference (MCLK, BCLK or

LRCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For

best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit -

should be selected.

The FLL output frequency is directly determined from FLLn_FRATIO, FLLn_OUTDIV and the real

number represented by N.K. The integer portion, N, is held in the FLLn_N register field (LSB = 1); the

fractional portion of N.K is held in the FLLn_K register field (MSB = 0.5).

The FLL output frequency is generated according to the following equation:

FOUT = (FVCO / FLLn_OUTDIV)

The FLL operating frequency, FVCO is set according to the following equation:

FVCO = (FREF x N.K x FLLn_FRATIO)

FREF is the input frequency, as determined by FLLn_REFCLK_DIV.

FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.

Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed

across the full range of device operating conditions.

In order to follow the above requirements for FVCO, the value of FLLn_OUTDIV should be selected

according to the desired output FOUT. The divider, FLLn_OUTDIV, must be set so that FVCO is in the

range 90-100MHz. The available divisions are integers from 4 to 64. Some typical settings of

FLLn_OUTDIV are noted in Table 110.

OUTPUT FREQUENCY FOUT

FLLn_OUTDIV

1.875 MHz - 2.0833 MHz

101111 (divide by 48)

2.8125 MHz - 3.125 MHz

011111 (divide by 32)

3.75 MHz - 4.1667 MHz

010111 (divide by 24)

5.625 MHz - 6.25 MHz

001111 (divide by 16)

11.25 MHz - 12.5 MHz

000111 (divide by 8)

18 MHz - 20 MHz

000100 (divide by 5)

22.5 MHz - 25 MHz

000011 (divide by 4)

Table 110 Selection of FLLn_OUTDIV

WM8994ECS/R 数据表(PDF) 202 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 202 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载