WM8994ECSSLASHR datasheet(204/363 Pages) CIRRUS

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WM8994

204

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R544 (0220h)

FLL1 Control (1)

FLL1_ENA

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step

of the FLL1 enable sequence, ie.

after the other FLL registers have

been configured.

R545 (0221h)

FLL1 Control (2)

13:8

FLL1_OUTDIV

[5:0]

000000

FLL1 FOUT clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(FOUT = FVCO / FLL1_OUTDIV)

2:0

FLL1_FRATIO

[2:0]

000

FLL1 FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

R546 (0222h)

FLL1 Control (3)

15:0

FLL1_K[15:0]

0000h

FLL1 Fractional multiply for FREF

(MSB = 0.5)

R547 (0223h)

FLL1 Control (4)

14:5

FLL1_N[9:0]

000h

FLL1 Integer multiply for FREF

(LSB = 1)

R548 (0224h)

FLL1 Control (5)

4:3

FLL1_REFCLK_

DIV [1:0]

FLL1 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference)

must be divided down to

<=13.5MHz.

For lower power operation, the

reference clock can be divided

down further if desired.

1:0

FLL1_REFCLK_

SRC [1:0]

FLL1 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK1

11 = BCLK1

Table 112 FLL1 Register Map

WM8994ECS/R 数据表(PDF) 204 Page - Cirrus Logic

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