WM8994ECSSLASHR datasheet(207/363 Pages) CIRRUS

207 / 363 page

WM8994

Rev 4.6

207

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R580 (0244h)

FLL2 Control (5)

12:7

FLL2_FRC_NCO

_VAL [5:0]

19h

FLL2 Forced oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for

free-running FLL modes only)

FLL2_FRC_NCO

FLL2 Forced control select

0 = Normal

1 = FLL2 oscillator controlled by

FLL2_FRC_NCO_VAL

(Note that this field is required for

free-running FLL modes only)

Table 114 FLL Free-Running Mode

GPIO OUTPUTS FROM FLL

For each FLL, the WM8994 has an internal signal which indicates whether the FLL Lock has been

achieved. The FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event -

see “Interrupts”.

The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See

“General Purpose Input/Output” for details of how to configure a GPIO pin to output the FLL Lock

signal.

The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the

FLL Clock may be output even if the FLL is not selected as the WM8994 SYSCLK source. The FLL

clocking configuration is illustrated in Figure 70.

See “General Purpose Input/Output” for details of how

to configure a GPIO pin to output the FLL Clock.

EXAMPLE FLL CALCULATION

The following example illustrates how to derive the FLL1 registers to generate 12.288 MHz output

(FOUT) from a 12.000 MHz reference clock (FREF):



Set FLL1_REFCLK_DIV in order to generate FREF <=13.5MHz:

FLL1_REFCLK_DIV = 00 (divide by 1)



Set FLL1_OUTDIV for the required output frequency as shown in Table 110:-

FOUT = 12.288 MHz, therefore FLL1_OUTDIV = 7h (divide by 8)



Set FLL1_FRATIO for the given reference frequency as shown in Table 111:

FREF = 12MHz, therefore FLL1_FRATIO = 0h (divide by 1)



Calculate FVCO as given by FVCO = FOUT x FLL1_OUTDIV:-

FVCO = 12.288 x 8 = 98.304MHz



Calculate N.K as given by N.K = FVCO / (FLL1_FRATIO x FREF):

N.K = 98.304 / (1 x 12) = 8.192



Determine FLL1_N and FLL1_K from the integer and fractional portions of N.K:-

FLL1_N is 8. FLL1_K is 0.192



Convert FLL1_K into integer format:

0.192 x 65536 = 12582.912 (decimal).



Round off to 12583 (decimal) and convert to hex:

12583 (decimal) = 3127 (hex).

FLL1_K = 3127h

WM8994ECS/R 数据表(PDF) 207 Page - Cirrus Logic

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