WM8994ECSSLASHR datasheet(209/363 Pages) CIRRUS

209 / 363 page

WM8994

Rev 4.6

209

SAMPLE RATE CONVERSION

The WM8994 supports two main digital audio interfaces, AIF1 and AIF2. These interfaces are

configured independently and may operate entirely asynchronously to each other. The WM8994

performs stereo full-duplex sample rate conversion between the audio interfaces, allowing digital

audio to be routed between the interfaces, and allowing asynchronous audio data to be mixed

together.

The Sample Rate Converters (SRCs) are configured automatically within the WM8994, and no user

settings are required. The SRCs are enabled automatically when required and are disabled at other

times. Synchronisation between the audio interfaces is not instantaneous when the clocking or sample

rate configurations are updated; the lock status of the SRCs is signalled via the GPIO or Interrupt

circuits, as described in “General Purpose Input/Output” and “Interrupts”.

Separate clocks can be used for AIF1 and AIF2, allowing asynchronous operation on these interfaces.

The digital mixing core is clocked by SYSCLK, which is linked to either AIF1CLK or AIF2CLK, as

described in “Clocking and Sample Rates”. The digital mixing core is, therefore, always synchronised

to AIF1, or to AIF2, or to both interfaces at once.

SAMPLE RATE CONVERTER 1 (SRC1)

SRC1 performs sample rate conversion of digital audio data input to the WM8994. Sample Rate

Conversion is required when digital audio data is received on an audio interface that is not

synchronised to the digital mixing core.

SRC1 is automatically configured on AIF1 or AIF2, depending on the selected Clocking and Sample

Rate configuration. Note that SRC1 cannot convert input data on AIF1 and AIF2 simultaneously.

Sample Rate conversion on AIF1 is only supported on TDM Timeslot 0.

The SRC1 Lock status indicates when audio data can be received on the interface channel that is not

synchronised to the digital mixing core. No audio will be present on this signal path until SRC1 Lock is

achieved.

SAMPLE RATE CONVERTER 2 (SRC2)

SRC2 performs sample rate conversion of digital audio data output from the WM8994. Sample Rate

Conversion is required when digital audio data is transmitted on an audio interface that is not

synchronised to the digital mixing core.

SRC2 is automatically configured on AIF1 or AIF2, depending on the selected Clocking and Sample

Rate configuration. Note that SRC2 cannot convert output data on AIF1 and AIF2 simultaneously.

Sample Rate conversion on AIF1 is only supported on TDM Timeslot 0.

The SRC2 Lock status indicates when audio data can be transmitted on the interface channel that is

not synchronised to the digital mixing core. No audio will be present on this signal path until SRC2

Lock is achieved.

SAMPLE RATE CONVERTER RESTRICTIONS

The following restrictions apply to the configuration of the WM8994 Sample Rate Converters.

No SRC on AIF1 Timeslot 1. Sample Rate Conversion on audio interface AIF1 is not supported on

the TDM Timeslot 1. Therefore, it is not possible to route digital audio between AIF1 Timeslot 1 and

AIF2, or to mix together audio from these interface paths. Note that this only applies when the SRC is

applied to AIF1.

Maximum of three sample rates in the system. The audio sample rate of AIF1 input and AIF1

output may be different to each other. The audio sample rate of AIF2 input and AIF2 output may be

different to each other. However, it is not possible to have four different sample rates operating

simultaneously, as this would require sample rate conversion in too many paths. A maximum of three

different sample rates can be supported in the system.

No SRC capability when using 88.2kHz or 96kHz AIF input (DAC playback). If either interface is

configured for 88.2kHz or 96kHz sample rate, then the digital mixing core must also be configured for

WM8994ECS/R 数据表(PDF) 209 Page - Cirrus Logic

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