WM8994ECSSLASHR datasheet(213/363 Pages) CIRRUS

213 / 363 page

WM8994

Rev 4.6

213

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R257 (0101h)

Control Interface

SPI_CONTRD

Enable continuous read mode in

SPI (3-wire/4-wire) modes

0 = Disabled

1 = Enabled

SPI_4WIRE

SPI control mode select

0 = 3-wire using bidirectional SDA

1 = 4-wire using SDOUT

SPI_CFG

SDA/SDOUT pin configuration

0 = CMOS

1 = Open Drain (SPI_4WIRE = 0)

1 = Wired ‘OR’ (SPI_4WIRE = 1)

AUTO_INC

Enables address auto-increment

(applies to 2-wire I2C mode only)

0 = Disabled

1 = Enabled

R1825 (0721h)

Pull Control (2)

CSNADDR_PD

CS/ADDR Pull-down enable

0 = Disabled

1 = Enabled

CIFMODE_PD

CIFMODE Pull-down enable

0 = Disabled

1 = Enabled

Table 118 Control Interface Configuration

2-WIRE (I2C) CONTROL MODE

In 2-wire (I2C) mode, the WM8994 is a slave device on the control interface; SCLK is a clock input,

while SDAT is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters)

on the same interface, the WM8994 transmits logic 1 by tri-stating the SDAT pin, rather than pulling it

high. An external pull-up resistor is required to pull the SDAT line high so that the logic 1 can be

recognised by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the address of each register in the WM8994). The

device ID is selectable on the WM8994, using the CS

¯¯ /ADDR pin as shown in Table 119. The LSB of

the Device ID is the Read/Write bit; this bit is set to logic 1 for

“Read” and logic 0 for “Write”.

An internal pull-down resistor is enabled by default on the CS

¯¯ /ADDR pin; this can be configured using

the CSNADDR_PD register bit described in Table 118.

¯¯ /ADDR

DEVICE ID

Low

0011 0100 (34h)

High

0011 0110 (36h)

Table 119 Control Interface Device ID Selection

The WM8994 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDAT while SCLK remains high. This indicates that a device ID, register

address and data will follow. The WM8994 responds to the start condition and shifts in the next eight

bits on SDAT (8-bit device ID, including Read/Write bit, MSB first). If the device ID received matches

the device ID of the WM8994, then the WM8994 responds by pulling SDAT low on the next clock

pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the WM8994 returns to

the idle condition and waits for a new start condition and valid address.

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