WM8994ECSSLASHR datasheet(217/363 Pages) CIRRUS

217 / 363 page

WM8994

Rev 4.6

217

4-WIRE (SPI) CONTROL MODE

The 4-wire control interface uses the CS

¯¯ , SCLK, SDA and SDOUT pins.

The SDOUT function must be enabled on one of the GPIO pins (see “General Purpose Input/Output”).

The Data Output pin, SDOUT, can be configured as CMOS or

‘Wired OR’, as described in Table 118.

In CMOS mode, SDOUT is driven low when not outputting register data bits. In

‘Wired OR’ mode,

SDOUT is undriven (high impedance) when not outputting register data bits.

In Write operations (R/W=0), this mode is the same as 3-wire mode described above.

In Read operations (R/W=1), the SDA pin is ignored following receipt of the valid register address.

SDOUT is driven by the WM8994.

When SPI Continuous Read mode is enabled (SPI_CONTRD = 1), the WM8994 will readback from

incremental register addresses as long as CS

¯¯ is held low and SCLK is toggled. In this mode, the

WM8994 will increment the readback address after the first 32 clock cycles, and will output data from

the next register address, and successive register addresses, MSB first, for as long as CS

¯¯ is held low

and SCLK is toggled.

An internal pull-down resistor is enabled by default on the CS

¯¯ /ADDR pin; this can be configured using

the CSNADDR_PD register bit described in Table 118.

The 4-wire control mode timing is illustrated in Figure 80 and Figure 81.

A14

A13

A12

SDA

SCLK

15-bit control register address

16-bit control register data

SDOUT

B15

B14

B13

R/W

Figure 80 4-Wire Readback (CMOS)

A14

A13

A12

SDA

SCLK

15-bit control register address

16-bit control register data

SDOUT

B15

B14

B13

R/W

undriven

Figure 81 4-Wire Readback (Wired-

‘OR’)

WM8994ECS/R 数据表(PDF) 217 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 217 Page - Cirrus Logic

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