WM8994ECSSLASHR datasheet(216/363 Pages) CIRRUS

216 / 363 page

WM8994

216

Rev 4.6

Device ID

MSByte Data N

(1)

LSByte Data N

MSByte Data 0

LSByte Data 0

MSByte Data N-1

LSByte Data N-1

Read from 'Last Register Address'

Read from 'Last Register Address+N'

Read from 'Last Register Address+N-1'

MSByte Data 1

LSByte Data 1

Read from 'Last Register Address+1'

Figure 78 Multiple Register Read from Last Address using Auto-increment

Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of

the data in the WM8994 register map faster than is possible with single register operations. The auto-

increment option is enabled when the AUTO_INC register bit is set. This bit is defined in Table 118.

Auto-increment is enabled by default.

3-WIRE (SPI) CONTROL MODE

The 3-wire control interface uses the CS

¯¯ , SCLK and SDA pins.

In 3-wire control mode, a control word consists of 32 bits. The first bit is the read/write bit (R/W), which

is followed by 15 address bits (A14 to A0) that determine which control register is accessed. The

remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register.

In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDA pin. A rising edge on

¯¯ latches in a complete control word consisting of the last 32 bits.

In Write operations (R/W=0), all SDA bits are driven by the controlling device.

In Read operations (R/W=1), the SDA pin is driven by the controlling device to clock in the register

address, after which the WM8994 drives the SDA pin to output the applicable data bits.

During data output, the SDA pin can be configured as CMOS or Open Drain, using the SPI_CFG

required to pull the SDA line high so that the logic 1 can be recognised by the master.

When SPI Continuous Read mode is enabled (SPI_CONTRD = 1), the WM8994 will readback from

incremental register addresses as long as CS

¯¯ is held low and SCLK is toggled. In this mode, the

WM8994 will increment the readback address after the first 32 clock cycles, and will output data from

the next register address, and successive register addresses, MSB first, for as long as CS

¯¯ is held low

and SCLK is toggled.

An internal pull-down resistor is enabled by default on the CS

¯¯ /ADDR pin; this can be configured using

the CSNADDR_PD register bit described in Table 118.

The 3-wire control mode timing is illustrated in Figure 79.

R/W

A14

A13

A12

SDA

SCLK

15-bit control register address

16-bit control register data

B15

B14

B13

Figure 79 3-Wire Serial Control Interface

WM8994ECS/R 数据表(PDF) 216 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 216 Page - Cirrus Logic

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