WM8994ECSSLASHR datasheet(212/363 Pages) CIRRUS

212 / 363 page

WM8994

212

Rev 4.6

CONTROL INTERFACE

The WM8994 is controlled by writing to its control registers. Readback is available for all registers.

The Control Interface can operate as either a 2-, 3- or 4-wire interface:



2-wire (I2C) mode uses pins SCLK and SDA



3-wire (SPI) mode uses pins CS

¯¯ /ADDR, SCLK and SDA



4-wire (SPI) mode uses pins CS

¯¯ /ADDR, SCLK, SDA and SDOUT

Readback is provided on the bi-directional pin SDA in 2-/3-wire modes. In 4-wire mode, the SDOUT

function must be enabled on one of the GPIO pins (see “General Purpose Input/Output”).

The WM8994 uses 15-bit register addresses and 16-bit data in all Control Interface modes.

Note that the Control Interface function can be supported with or without system clocking. Where

possible, the register map access is synchronised with SYSCLK in order to ensure predictable

operation of cross-domain functions.

See “Clocking and Sample Rates” for further details of Control

Interface clocking.

SELECTION OF CONTROL INTERFACE MODE

The WM8994 Control Interface Mode is determined by the logic level on the CIFMODE pin, as shown

in Table 117. An internal pull-down resistor is enabled by default on the CIFMODE pin; this can be

configured using the CIFMODE_PD register bit described in Table 118.

CIFMODE

INTERFACE FORMAT

Low

2 wire (I2C) Mode

High

3- or 4- wire (SPI) Modes

Table 117 Control Interface Mode Selection

In 2-wire (I2C) Control Interface mode, Auto-Increment mode may be selected. This enables multiple

write and multiple read operations to be scheduled faster than is possible with single register

operations. The auto-increment option is enabled when the AUTO_INC register bit is set. This bit is

defined in Table 118. Auto-increment is enabled by default.

In SPI modes, 3-wire or 4-wire operation may be selected using the SPI_4WIRE register bit.

In SPI modes, the Continuous Read mode may be selected using the SPI_CONTRD bit. This enables

multiple register read operations to be scheduled faster than is possible with single register

operations. When SPI_CONTRD is set, the WM8994 will readback from incremental register

addresses as long as CS

¯¯ is held low and SCLK is toggled.

In 3-wire (SPI) mode, register readback is provided using the bi-directional pin SDA. During data

output, the SDA pin can be configured as CMOS or Open Drain, using the SPI_CFG register bit.

In 4-wire (SPI) mode, register readback is provided using SDOUT. The SDOUT pin may be configured

as CMOS o

r as ‘Wired OR’ using the SPI_CFG bit. In CMOS mode, SDOUT is driven low when not

outputting register data. In ‘Wired OR’ mode, SDOUT is undriven (high impedance) when not

outputting register data bits.

The Control Interface configuration bits are described in Table 118.

WM8994ECS/R 数据表(PDF) 212 Page - Cirrus Logic

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