WM8994ECSSLASHR datasheet(211/363 Pages) CIRRUS

211 / 363 page

WM8994

Rev 4.6

211

SAMPLE RATE CONVERTER CONFIGURATION ERROR INDICATION

The WM8994 verifies the register settings relating to Clocking, Sample Rates and Sample Rate

Conversion. If an invalid configuration is attempted, then the SR_ERROR register will indicate the

error by showing a non-zero value. This read-only field may be checked to confirm that the WM8994

can support the selected Clocking and Sample Rate settings.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R530 (0212h)

Rate Status

3:0

SR_ERROR

[3:0]

0000

Sample Rate Configuration status

Indicates an error with the register settings

related to sample rate configuration

0000 = No errors

0001 = Invalid sample rate

0010 = Invalid AIF divide

0011 = ADC and DAC divides both set in an

interface

0100 = Invalid combination of AIF divides

and sample-rate

0101 = Invalid set of enables for 96kHz

mode

0110 = Invalid SYSCLK rate (derived from

AIF1CLK_RATE or AIF2CLK_RATE)

0111 = Mixed ADC and DAC rates in

SYSCLK AIF when AIFs are asynchronous

1000 = Invalid combination of sample rates

when both AIFs are from the same clock

source

1001 = Invalid combination of mixed

ADC/DAC AIFs when both from the same

clock source

1010 = AIF1DAC2 (Timeslot 1) ports enabled

when SRCs connected to AIF1

Table 116 Sample Rate Converter Configuration Status

WM8994ECS/R 数据表(PDF) 211 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 211 Page - Cirrus Logic

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