WM8994ECSSLASHR datasheet(210/363 Pages) CIRRUS

210 / 363 page

WM8994

210

Rev 4.6

this sample rate. Sample Rate Conversion cannot be supported in this mode, therefore AIF output is

not supported at any sample rate under these conditions.

Restricted Sample Rate options when AIF1 and AIF2 are synchronised. When the same clock

source is used for AIF1CLK and AIF2CLK, and mixed sample rates are selected on both interfaces,

then the DAC sample rate of one interface must be the same as the ADC sample rate of the other.



If AIF1CLK_SRC = AIF2CLK_SRC



And AIF1DAC_DIV

≠ AIF1ADC_DIV



And AIF2DAC_DIV

≠ AIF2ADC_DIV



Then the DAC sample rate of one interface must be the same as the ADC sample rate of

the other.

Restricted Sample Rate options when AIF1 and AIF2 are not synchronised. When a different

clock source is used for AIF1CLK and AIF2CLK, then the AIF to which the SYSCLK is synchronised

cannot be mixed sample rates.



If AIF1CLK_SRC

≠ AIF2CLK_SRC



And SYSCLK_SRC =0



Then AIF1DAC_DIV and AIF1ADC_DIV must be set to 000



If AIF1CLK_SRC

≠ AIF2CLK_SRC



And SYSCLK_SRC =1



Then AIF2DAC_DIV and AIF2ADC_DIV must be set to 000

WM8994ECS/R 数据表(PDF) 210 Page - Cirrus Logic

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