WM8994ECSSLASHR datasheet(214/363 Pages) CIRRUS

214 / 363 page

WM8994

214

Rev 4.6

If the device ID matches the device ID of the WM8994, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDAT while

SCLK remains high. After receiving a complete address and data sequence the WM8994 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDAT changes while SCLK is high), the device returns

to the idle condition.

The WM8994 supports the following read and write operations:



Single write



Single read



Multiple write using auto-increment



Multiple read using auto-increment

The sequence of signals associated with a single register write operation is illustrated in Figure 72.

A15

SDA

SCLK

device ID

data bits B15

– B8

B15

Note: The SDA pin is used as input for the control register address and data; SDA is

pulled low by the receiving device to provide the acknowledge (ACK) response

R/W

data bits B7

– B0

START

(Write)

ACK

STOP

ACK

Figure 72 Control Interface 2-wire (I2C) Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 73.

device ID

B15

data bits B15

– B8

ACK

R/W

(Read)

data bits B7

– B0

ACK

STOP

ACK

A15

SDA

SCLK

device ID

Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses

R/W

– A8

START

(Write)

ACK

Rpt

START

– A0

Figure 73 Control Interface 2-wire (I2C) Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 120.

Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.

This feature is enabled by default, as noted in Table 118.

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