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WM8994ECS/R 数据表(PDF) 208 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 208 Page - Cirrus Logic |
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208 / 363 page  WM8994 208 Rev 4.6 EXAMPLE FLL SETTINGS Table 115 provides example FLL settings for generating common SYSCLK frequencies from a variety of low and high frequency reference inputs. FSOURCE FOUT FREF Divider N.K FRATIO FVCO OUTDIV FLLn_N FLLn_K 32 kHz 12.288 MHz 1 192 16 98.304 MHz 8 0C0h 0000h 32 kHz 11.2896 MHz 1 176.4 16 90.3168 MHz 8 0B0h 6666h 32.768 kHz 12.288 MHz 1 187.5 16 98.304 MHz 8 0BBh 8000h 32.768 kHz 11.2896 MHz 1 172.2656 16 90.3168 MHz 8 0ACh 4400h 44.1 kHz 11.2896 MHz 1 128 16 90.3168 MHz 8 080h 0000h 48 kHz 12.288 MHz 1 128 16 98.304 MHz 8 080h 0000h 128 kHz 2.048 MHz 1 192 4 98.304 MHz 48 0C0h 0000h 128 kHz 12.288 MHz 1 192 4 98.304 MHz 8 0C0h 0000h 512 kHz 2.048 MHz 1 96 2 98.304 MHz 48 060h 0000h 512 kHz 12.288 MHz 1 96 2 98.304 MHz 8 060h 0000h 1.4112 MHz 11.2896 MHz 1 64 1 90.3168 MHz 8 040h 0000h 2.8224 MHz 11.2896 MHz 1 32 1 90.3168 MHz 8 020h 0000h 1.536 MHz 12.288 MHz 1 64 1 98.304 MHz 8 040h 0000h 3.072 MHz 12.288 MHz 1 32 1 98.304 MHz 8 020h 0000h 11.2896 MHz 12.288 MHz 1 8.7075 1 98.304 MHz 8 008h B51Eh 12 MHz 11.2896 MHz 1 7.5264 1 90.3168 MHz 8 007h 86C2h 12 MHz 12.288 MHz 1 8.192 1 98.304 MHz 8 008h 3127h 12.288 MHz 12.288 MHz 1 8 1 98.304 MHz 8 008h 0000h 12.288 MHz 11.2896 MHz 1 7.35 1 90.3168 MHz 8 007h 599Ah 13 MHz 12.288 MHz 1 7.5618 1 98.304 MHz 8 007h 8FD5h 13 MHz 11.2896 MHz 1 6.9474 1 90.3168 MHz 8 006h F28Ch 19.2 MHz 12.288 MHz 2 10.24 1 98.304 MHz 8 00Ah 3D71h 19.2 MHz 11.2896 MHz 2 9.408 1 90.3168 MHz 8 009h 6873h 24 MHz 11.2896 MHz 2 7.5264 1 90.3168 MHz 8 007h 86C2h 24 MHz 12.288 MHz 2 8.192 1 98.304 MHz 8 008h 3127h 26 MHz 11.2896 MHz 2 6.9474 1 90.3168 MHz 8 006h F28Ch 26 MHz 12.288 MHz 2 7.5618 1 98.304 MHz 8 007h 8FD5h 27 MHz 11.2896 MHz 2 6.6901 1 90.3168 MHz 8 006h B0ADh 27 MHz 12.288 MHz 2 7.2818 1 98.304 MHz 8 007h 4823h FOUT = (FSOURCE / FREF Divider) * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N and FLLn_K registers as shown above. See Table 112 and Table 113 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 115 Example FLL Settings |
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