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WM8994ECS/R 数据表(PDF) 220 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 220 Page - Cirrus Logic |
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220 / 363 page  WM8994 220 Rev 4.6 WSEQ_DATA_STARTn is a 4-bit field which identifies the LSB position within the selected Control Register to which the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 will select bit 4 as the LSB position; in this case, 4-bit data would be written to bits 7:4. WSEQ_DATA_WIDTHn is a 3-bit field which identifies the width of the data block to be written. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the need for read-modify-write procedures. Values of 0 to 7 correspond to data widths of 1 to 8 respectively. For example, setting WSEQ_DATA_WIDTHn = 010 will cause a 3-bit data block to be written. Note that the maximum value of this field corresponds to an 8-bit data block; writing to register fields greater than 8 bits wide must be performed using two separate operations of the Control Write Sequencer. WSEQ_DELAYn is a 4-bit field which controls the waiting time between the current step and the next step in the sequence i.e. the delay occurs after the write in which it was called. The total delay time per step (including execution) is defined below, giving a useful range of execution/delay times from 562 s up to 2.048s per step: T = k × (2 WSEQ_DELAY + 8) where k = 62.5 s (under recommended operating conditions) WSEQ_EOSn is a 1-bit field which indicates the End of Sequence. If this bit is set, then the Control Write Sequencer will automatically stop after this step has been executed. The register definitions for Step 0 are described in Table 122. The equivalent definitions also apply to Step 1 through to Step 127, in the subsequent register address locations. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12288 (3000h) Write Sequencer 0 13:0 WSEQ_ADDR 0 [13:0] 0000h Control Register Address to be written to in this sequence step. R12289 (3001h) Write Sequencer 1 7:0 WSEQ_DATA 0 [7:0] 00h Data to be written in this sequence step. When the data width is less than 8 bits, then one or more of the MSBs of WSEQ_DATAn are ignored. It is recommended that unused bits be set to 0. R12290 (3002h) Write Sequencer 2 10:8 WSEQ_DATA _WIDTH0 [2:0] 000 Width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 3:0 WSEQ_DATA _START0 [3:0] 0000 Bit position of the LSB of the data block written in this sequence step. 0000 = Bit 0 … 1111 = Bit 15 |
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