WM8994ECSSLASHR datasheet(223/363 Pages) CIRRUS

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WM8994

Rev 4.6

223

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

0 (00h)

R57 (0039h)

5 bits

Bit 2

1Bh

STARTUP_BIAS_ENA = 1

VMID_BUF_ENA = 1

VMID_RAMP[1:0] = 11b

(delay = 0.5625ms)

1 (01h)

R1 (0001h)

3 bits

Bit 0

03h

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 32.5ms)

2 (02h)

R76 (004Ch)

1 bit

Bit 15

01h

CP_ENA = 1

(delay = 4.5ms)

3 (03h)

R1 (0001h)

2 bits

Bit 8

03h

HPOUT1R_ENA = 1

HPOUT1L_ENA = 1

(delay = 0.5625ms)

4 (04h)

R96 (0060h)

5 bits

Bit 1

11h

HPOUT1R_DLY = 1

HPOUT1L_DLY = 1

(delay = 0.5625ms)

5 (05h)

R84 (0054h)

6 bits

Bit 0

33h

DCS_ENA_CHAN_0 = 1

DCS_ENA_CHAN_1 = 1

DCS_TRIG_STARTUP_0 = 1

DCS_TRIG_STARTUP_1 = 1

(delay = 256.5ms)

6 (06h)

R255 (00FFh)

1 bit

Bit 0

00h

Dummy Write for expansion

(delay = 0.5625ms)

7 (07h)

R96 (0060h)

6 bits

Bit 2

3Bh

HPOUT1R_OUTP = 1

HPOUT1R_RMV_SHORT =1

HPOUT1_DLY = 1

HPOUT1L_OUTP = 1

HPOUT1L_RMV_SHORT = 1

(delay = 0.5625ms)

Table 123 Headphone Cold Start-Up Default Sequence

Headphone Warm Start-Up

The Headphone Warm Start-Up sequence can be initiated by writing 8108h to Register 272 (0110h).

This single operation starts the Control Write Sequencer at Index Address 8 (08h) and executes the

sequence defined in Table 124.

This sequence takes approximately 40ms to run.

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

8 (08h)

R57 (0039h)

5 bits

Bit 2

1Bh

STARTUP_BIAS_ENA = 1

VMID_BUF_ENA = 1

VMID_RAMP[1:0] = 11b

(delay = 0.5625ms)

9 (09h)

R1 (0001h)

3 bits

Bit 0

03h

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 32.5ms)

10 (0Ah)

R76 (004Ch)

1 bits

Bit 15

01h

CP_ENA = 1

(delay = 4.5ms)

11 (0Bh)

R1 (0001h)

2 bits

Bit 8

03h

HPOUT1R_ENA = 1

HPOUT1L_ENA = 1

(delay = 0.5625ms)

WM8994ECS/R 数据表(PDF) 223 Page - Cirrus Logic

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WM8994ECS/R 数据表(PDF) 223 Page - Cirrus Logic

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