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WM8994ECS/R 数据表(PDF) 224 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 224 Page - Cirrus Logic

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WM8994
224
Rev 4.6
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
12 (0Ch)
R96 (0060h)
5 bits
Bit 1
11h
0h
0b
HPOUT1R_DLY = 1
HPOUT1L_DLY = 1
(delay = 0.5625ms)
13 (0Dh)
R84 (0054h)
2 bits
Bit 0
03h
0h
0b
DCS_ENA_CHAN_0 = 1
DCS_ENA_CHAN_1 = 1
(delay = 0.5625ms)
14 (0Eh)
R255 (00FFh)
1 bits
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5625ms)
15 (0Fh)
R96 (0060h)
6 bits
Bit 2
3Bh
0h
1b
HPOUT1R_OUTP = 1
HPOUT1R_RMV_SHORT =1
HPOUT1_DLY = 1
HPOUT1L_OUTP = 1
HPOUT1L_RMV_SHORT = 1
(delay = 0.5625ms)
Table 124 Headphone Warm Start-Up Default Sequence
Speaker Start-Up
The Speaker Start-Up sequence can be initiated by writing 8110h to Register 272 (0110h). This single
operation starts the Control Write Sequencer at Index Address 16 (10h) and executes the sequence
defined in Table 125.
This sequence takes approximately 34ms to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
16 (10h)
R57 (39h)
5 bits
Bit 2
1Bh
0h
0b
STARTUP_BIAS_ENA = 1
VMID_BUF_ENA = 1
VMID_RAMP[1:0] = 11b
(delay = 0.5625ms)
17 (11h)
R1 (01h)
3 bits
Bit 0
03h
9h
0b
BIAS_ENA = 1
VMID_SEL[1:0] = 01b
(delay = 32.5ms)
18 (12h)
R1 (01h)
2 bits
Bit 12
03h
0h
1b
SPKOUTL_ENA = 1
SPKOUTR_ENA = 1
(delay = 0.5625ms)
Table 125 Speaker Start-Up Default Sequence
Earpiece Start-Up
The Earpiece Start-Up sequence can be initiated by writing 8113h to Register 272 (0110h). This single
operation starts the Control Write Sequencer at Index Address 19 (13h) and executes the sequence
defined in Table 126.
This sequence takes approximately 259ms to run.



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