WM8994ECSSLASHR datasheet(228/363 Pages) CIRRUS

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WM8994

228

Rev 4.6

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

56 (38h)

R56 (38h)

1 bit

Bit 7

00h

LINEOUT_VMID_BUF_ENA = 0

(delay = 0.5625ms)

57 (39h)

R55 (37h)

1 bit

Bit 0

00h

VROI = 0

(delay = 0.5625ms)

58 (3Ah)

R57 (39h)

6 bits

Bit 1

00h

BIAS_SRC = 0

STARTUP_BIAS_ENA = 0

VMID_BUF_ENA = 0

VMID_RAMP[1:0] = 00b

(delay = 0.5625ms)

Table 129 Generic Shut-Down Default Sequence

LDO REGULATORS

The WM8994 provides two integrated Low Drop-Out Regulators (LDOs). These are provided to

generate the appropriate power supplies for internal circuits, simplifying and reducing the

requirements for external supplies and associated components. A reference circuit powered by

AVDD2 ensures the accuracy of the LDO regulator voltage settings.

Note that the integrated LDOs are only intended for generating the AVDD1 and DCVDD supply rails

for the WM8994; they are not suitable for powering any additional or external loads.

LDO1 is intended for generating AVDD1 - the primary analogue power domain of the WM8994. LDO1

is powered by LDO1VDD and

is enabled when a logic ‘1’ is applied to the LDO1ENA pin. The logic

level is determined with respect to the DBVDD voltage domain. The LDO1 start-up time is dependent

on the external AVDD1 and VREFC capacitors; the start-up time is illustrated in Figure 84 and defined

in Table 130 for the recommended external component conditions.

When LDO1 is enabled, the output voltage is controlled by the LDO1_VSEL register field. Note that

the LDO1 voltage difference LDO1VDD - AVDD1 must be higher than the LDO1 Drop-Out voltage

(see “Electrical Characteristics”).

LDO1 is disabled when a logic ‘0’ is applied to the LDO1ENA pin. After LDO1 has been disabled,

there is a minimum delay, defined as the LDO1 Cycle Time, during which LDO1 should not be re-

enabled. The LDO1 Cycle Time is illustrated in Figure 84 and defined in Table 130 for the

recommended external component conditions.

When LDO1 is disabled, the output can be left floating or can be actively discharged, depending on

the LDO1_DISCH control bit.

It is possible to supply AVDD1 from an external supply. If AVDD1 is supplied externally, then LDO1

should be disabled, and the LDO1 output left floating (LDO1DISCH = 0). Note that the LDO1VDD

voltage must be greater than or equal to AVDD1; this ensures that there is no leakage path through

the LDO for the external supply.

Note that the WM8994 can operate with AVDD1 tied to 0V; power consumption may be reduced, but

the analogue audio functions will not be supported.

LDO2 is intended for generating the DCVDD power domain which supplies the digital core functions

on the WM8994. LDO2 is powered by LDO2VDD and

is enabled when a logic ‘1’ is applied to the

LDO2ENA pin. The logic level is determined with respect to the DBVDD voltage domain. The LDO2

start-up time is dependent on the external DCVDD and VREFC capacitors; the start-up time is

illustrated in Figure 84 and defined in Table 130 for the recommended external component conditions.

When LDO2 is enabled, the output voltage is controlled by the LDO2_VSEL register field.

O2 is disabled when a logic ‘0’ is applied to the LDO2ENA pin. After LDO2 has been disabled,

there is a minimum delay, defined as the LDO2 Cycle Time, during which LDO2 should not be re-

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WM8994ECS/R 数据表(PDF) 228 Page - Cirrus Logic

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