WM8994ECSSLASHR datasheet(229/363 Pages) CIRRUS

229 / 363 page

WM8994

Rev 4.6

229

enabled. The LDO2 Cycle Time is illustrated in Figure 84 and defined in Table 130 for the

recommended external component conditions.

When LDO2 is disabled, the output can be left floating or can be actively discharged, depending on

the LDO2_DISCH control bit.

It is possible to supply DCVDD from an external supply. If DCVDD is supplied externally, the

LDO2ENA and LDO2DISCH bits should be set to 0. Note that the DBVDD voltage must be greater

than or equal to DCVDD; this ensures that there is no leakage path through the LDO for the external

supply.

An internal pull-down resistor is enabled by default on the LDO1ENA and LDO2ENA pins. These pull-

down resistors can be configured using the register bits described in Table 131.

Decoupling capacitors should be connected to the voltage reference pin, VREFC, and also to the LDO

outputs, AVDD1 and DCVDD. See “Applications Information” for further details.

The LDO Regulator connections and controls are illustrated in Figure 83. The register controls are

defined in Table 131.

AVDD2

VREFC

Voltage

Reference

LDO1VDD

LDO1

AVDD1

LDO2VDD

LDO2

DCVDD

WM8994 Digital

Core Supply

WM8994

Analogue Supply

LDO1ENA

LDO2ENA

LDO1_VSEL[2:0]

LDO1_DISCH

LDO2_VSEL[1:0]

LDO2_DISCH

Figure 83 LDO Regulators

LDOnENA

DCVDD or

AVDD1

tLDOn_CYCLE

tLDOn_START

Figure 84 LDO Enable/Disable Timing Diagram

WM8994ECS/R 数据表(PDF) 229 Page - Cirrus Logic

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