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WM8994ECS/R 数据表(PDF) 226 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 226 Page - Cirrus Logic |
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226 / 363 page  WM8994 226 Rev 4.6 WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 32 (20h) R30 (1Eh) 2 bits Bit 5 00h 0h 0b LINEOUT1P_MUTE = 0 LINEOUT1N_MUTE = 0 (delay = 0.5625ms) 33 (21h) R30 (1Eh) 2 bits Bit 1 00h 0h 1b LINEOUT2P_MUTE = 0 LINEOUT2N_MUTE = 0 (delay = 0.5625ms) Table 127 Line Output Start-Up Default Sequence Speaker and Headphone Fast Shut-Down The Speaker and Headphone Fast Shut-Down sequence can be initiated by writing 8122h to Register 272 (0110h). This single operation starts the Control Write Sequencer at Index Address 34 (22h) and executes the sequence defined in Table 128. This sequence takes approximately 37ms to run. WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 34 (22h) R96 (60h) 7 bits Bit 1 00h 0h 0b HPOUT1R_DLY = 0 HPOUT1R_OUTP = 0 HPOUT1R_RMV_SHORT = 0 HPOUT1L_DLY = 0 HPOUT1L_OUTP = 0 HPOUT1L_RMV_SHORT = 0 (delay = 0.5625ms) 35 (23h) R84 (54h) 2 bits Bit 0 00h 0h 0b DCS_ENA_CHAN_0 = 0 DCS_ENA_CHAN_1 = 0 (delay = 0.5625ms) 36 (24h) R1 (01h) 2 bits Bit 8 00h 0h 0b HPOUT1R_ENA = 0 HPOUT1L_ENA = 0 (delay = 0.5625ms) 37 (25h) R76 (4Ch) 1 bit Bit 15 00h 0h 0b CP_ENA = 0 (delay = 0.5625ms) 38 (26h) R1 (01h) 2 bits Bit 12 00h 0h 0b SPKOUTL_ENA = 0 SPKOUTR_ENA = 0 (delay = 0.5625ms) 39 (27h) R57 (39h) 6 bits Bit 1 37h 0h 0b BIAS_SRC = 1 STARTUP_BIAS_ENA = 1 VMID_BUF_ENA = 1 VMID_RAMP[1:0] = 11b (delay = 0.5625ms) 40 (28h) R1 (01h) 3 bits Bit 0 00h 9h 0b BIAS_ENA = 0 VMID_SEL = 00b (delay = 32.5ms) 41 (29h) R57 (39h) 6 bits Bit 1 00h 0h 1b BIAS_SRC = 0 STARTUP_BIAS_ENA = 0 VMID_BUF_ENA = 0 VMID_RAMP[1:0] = 00b (delay = 0.5625ms) Table 128 Speaker and Headphone Fast Shut-Down Default Sequence |
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