WM8994ECSSLASHR datasheet(221/363 Pages) CIRRUS

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WM8994

Rev 4.6

221

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12291

(3003h)

Write

Sequencer 3

WSEQ_EOS0

End of Sequence flag. This bit indicates

whether the Control Write Sequencer

should stop after executing this step.

0 = Not end of sequence

1 = End of sequence (Stop the

sequencer after this step).

3:0

WSEQ_DELA

Y0 [3:0]

0000

Time delay after executing this step.

Total time per step (including execution)

= 62.5µs × (2WSEQ_DELAY + 8)

Table 122 Write Sequencer Control - Programming a Sequence

Note that a ‘Dummy’ write can be inserted into a control sequence by commanding the sequencer to

write a value of 0 to bit 0 of Register R255 (00FFh). This is effectively a write to a non-existent register

location. This can be used in order to create placeholders ready for easy adaptation of a control

sequence. For example, a sequence could be defined to power-up a mono signal path from DACL to

headph

one, with a ‘dummy’ write included to leave space for easy modification to a stereo signal path

configuration. Dummy writes can also be used in order to implement additional time delays between

123 and Table 124.

In summary, the Control Register to be written is set by the WSEQ_ADDRn field. The data bits that

are written are determined by a combination of WSEQ_DATA_STARTn, WSEQ_DATA_WIDTHn and

WSEQ_DATAn. This is illustrated below for an example case of writing to the VMID_SEL field within

In this example, the Start Position is bit 01 (WSEQ_DATA_STARTn = 0001b) and the Data width is 2

bits (WSEQ_DATA_WIDTHn = 0001b). With these settings, the Control Write Sequencer would

update the Control Register R1 [2:1] with the contents of WSEQ_DATAn [1:0].

b15

b14

b13

b12

b11

b10

b09

b08

b07

b06

b05

b04

b03

b02

b01

b00

R1 (0001h)

Power

Management (1)

LSB position = b01

WSEQ_DATA_STARTn = 0001

Data Width = 2 bits

WSEQ_DATA_WIDTHn = 0001

WSEQ_DATAn (8 bits)

b07

b06

b05

b04

b03

b02

b01

b00

WSEQ_DATA_WIDTHn = 2 bits.

Therefore, only the Least Significant 2 bits are valid. Bits 02 to 07 are discarded

XX X X X X

VMID_SEL

Figure 82 Control Write Sequencer Example

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