WM8994ECSSLASHR datasheet(201/363 Pages) CIRRUS

201 / 363 page

WM8994

Rev 4.6

201

CONTROL INTERFACE CLOCKING

the SYSCLK_SRC register selects either AIF1CLK or AIF2CLK as the applicable SYSCLK source.

When AIF1CLK is the SYSCLK source (ie. SYSCLK_SRC = 0), and AIF1CLK_ENA = 1, then an

active clock source for AIF1CLK must be present for control interface clocking. If the AIF1CLK source

is stopped, then AIF1CLK_ENA must be set to 0 for control register access.

When AIF2CLK is the SYSCLK source (ie. SYSCLK_SRC = 1), and AIF2CLK_ENA = 1, then an

active clock source for AIF2CLK must be present for control interface clocking. If the AIF2CLK source

is stopped, then AIF2CLK_ENA must be set to 0 for control register access.

FREQUENCY LOCKED LOOP (FLL)

Two integrated FLLs are provided to support the clocking requirements of the WM8994. These can be

enabled and configured independently according to the available reference clocks and the application

requirements. The reference clock may be a high frequency (eg. 12.288MHz) or low frequency (eg.

32.768kHz).

The FLL is tolerant of jitter and may be used to generate a stable AIF clock from a less stable input

reference. The FLL characteristics are summarised in “Electrical Characteristics”. Note that the FLL

can be used to generate a free-running clock in the absence of an external reference source. This is

described in the “Free-Running FLL Clock” section below.

The input reference for FLL1 is selected using FLL1_REFCLK_SRC. The available options are

MCLK1,

MCLK2,

BCLK1

LRCLK1.

The

input

reference

for

FLL2

selected

using

FLL2_REFCLK_SRC. The available options are MCLK1, MCLK2, BCLK2 or LRCLK2. The FLL input

reference configuration is illustrated in Figure 70.

GPIO2/MCLK2

MCLK1

FLL1

LRCLK1

BCLK1

FLL2

LRCLK2

BCLK2

FLL1_REFCLK_SRC

FLL2_REFCLK_SRC

Figure 70 FLL Input Reference Selection

The following description is applicable to FLL1 and FLL2. The associated register control fields are

described in Table 112 for FLL1 and Table 113 for FLL2.

The FLL control registers are illustrated in Figure 71.

FVCO

FOUT

90MHz < Fvco < 100MHz

FLL_OUTDIV = 4

… 64

FLL_FRATIO = 1, 2, 4, 8, 16

Multiply by

N.K

N.K = Real number

Divide by

FLL_REFCLK_DIV

FREF

FLL_REFCLK_DIV = 1, 2, 4, 8

FREF<13.5MHz

Divide by

FLL_OUTDIV

Multiply by

FLL_FRATIO

FLL Source

Figure 71 FLL Configuration

WM8994ECS/R 数据表(PDF) 201 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 201 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载