数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

WM8994ECS/R 数据表(PDF) 199 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 199 Page - Cirrus Logic

Back Button WM8994ECS/R Datasheet HTML 195Page - Cirrus Logic WM8994ECS/R Datasheet HTML 196Page - Cirrus Logic WM8994ECS/R Datasheet HTML 197Page - Cirrus Logic WM8994ECS/R Datasheet HTML 198Page - Cirrus Logic WM8994ECS/R Datasheet HTML 199Page - Cirrus Logic WM8994ECS/R Datasheet HTML 200Page - Cirrus Logic WM8994ECS/R Datasheet HTML 201Page - Cirrus Logic WM8994ECS/R Datasheet HTML 202Page - Cirrus Logic WM8994ECS/R Datasheet HTML 203Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 199 / 363 page
background image
WM8994
Rev 4.6
199
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (0002h)
Power
Management
(2)
11
OPCLK_ENA
0
GPIO Clock Output (OPCLK) Enable
0 = Disabled
1 = Enabled
R520 (0208h)
Clocking (1)
4
TOCLK_ENA
0
Slow Clock (TOCLK) Enable
0 = Disabled
1 = Enabled
This clock is required for zero-cross
timeout.
3
AIF1DSPCLK
_ENA
0
AIF1 Processing Clock Enable
0 = Disabled
1 = Enabled
2
AIF2DSPCLK
_ENA
0
AIF2 Processing Clock Enable
0 = Disabled
1 = Enabled
1
SYSDSPCLK_
ENA
0
Digital Mixing Processor Clock Enable
0 = Disabled
1 = Enabled
0
SYSCLK_SRC
0
SYSCLK Source Select
0 = AIF1CLK
1 = AIF2CLK
R521 (0209h)
Clocking (2)
10:8
TOCLK_DIV
000
Slow Clock (TOCLK ) Divider
(Sets TOCLK rate relative to 256kHz.)
000 = Divide by 256 (1kHz)
001 = Divide by 512 (500Hz)
010 = Divide by 1024 (250Hz)
011 = Divide by 2048 (125Hz)
100 = Divide by 4096 (62.5Hz)
101 = Divide by 8192 (31.2Hz)
110 = Divide by 16384 (15.6Hz)
111 = Divide by 32768 (7.8Hz)
6:4
DBCLK_DIV
000
De-bounce Clock (DBCLK) Divider
(Sets DBCLK rate relative to 256kHz.)
000 = Divide by 256 (1kHz)
001 = Divide by 2048 (125Hz)
010 = Divide by 4096 (62.5Hz)
011 = Divide by 8192 (31.2Hz)
100 = Divide by 16384 (15.6Hz)
101 = Divide by 32768 (7.8Hz)
110 = Divide by 65536 (3.9Hz)
111 = Divide by 131072 (1.95Hz)
2:0
OPCLK_DIV
000
GPIO Output Clock (OPCLK) Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com