WM8994ECSSLASHR datasheet(193/363 Pages) CIRRUS

193 / 363 page

WM8994

Rev 4.6

193

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R512 (0200h)

AIF 1

Clocking (1)

4:3

AIF1CLK_SR

AIF1CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

AIF1CLK_INV

AIF1CLK Invert

0 = AIF1CLK not inverted

1 = AIF1CLK inverted

AIF1CLK_DIV

AIF1CLK Divider

0 = AIF1CLK

1 = AIF1CLK / 2

AIF1CLK_EN

AIF1CLK Enable

0 = Disabled

1 = Enabled

Table 105 AIF1CLK Enable

AIF1 CLOCKING CONFIGURATION

The WM8994 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The AIF1

clocking configuration is selected using 4 control fields, which are set according to the required AIF

digital audio sample rate, and the ADC/DAC clocking rate.

The AIF1_SR register is set according to the AIF1 sample rate. Note that 88.2kHz and 96kHz modes

are supported for AIF1 input (DAC playback) only.

The AIF1CLK_RATE register is set according to the ratio of AIF1CLK to the AIF1 sample rate. Note

that there a some restrictions on the supported clocking ratios, depending on the selected sample rate

and operating conditions. The supported configurations are detailed in the “Digital Microphone

Interface

”, “Analogue to Digital Converter (ADC)” and “Digital to Analogue Converter (DAC)” sections,

according to each applicable function.

The audio interface can support different sample rates for the input data (DAC path) and output data

(ADC path) simultaneously. In this case, the AIF1_SR and AIF1CLK_RATE fields should be set

according to the faster of the two sample rates.

When different sample rates are used for input data (DAC path) and output data (ADC path), the

clocking of the slower path is set using AIF1DAC_DIV (if the AIF input path has the slower sample

rate) or AIF1ADC_DIV (if the AIF output path has the slower sample rate). The appropriate divider is

set according to the ratio of the two sample rates.

For example, if AIF1 input uses 48kHz sample rate, and AIF1 output uses 8kHz, then AIF1ADC_DIV

should be set to 110b (divide by 6).

Note that the audio interface cannot support every possible combination of input and output sample

rate simultaneously, but only where the ratio of the sample rates matches the available AIF1ADC_DIV

or AIF1DAC_DIV divider settings.

Note that the WM8994 performs sample rate conversion, where necessary, to provide digital mixing

and interconnectivity between the Audio Interfaces and the DSP Core functions. One stereo Sample

Rate Converter (SRC) is provided for audio input; a second stereo SRC is provided for audio output.

Each SRC is automatically configured on AIF1 or AIF2, depending on the selected Clocking and

Sample Rate settings. The WM8994 cannot support configurations that would require SRC on the

input or output paths of both interfaces simultaneously. See “Sample Rate Conversion” for further

details.

WM8994ECS/R 数据表(PDF) 193 Page - Cirrus Logic

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