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WM8994ECS/R 数据表(PDF) 249 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 249 Page - Cirrus Logic

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WM8994
Rev 4.6
249
REG
NAME
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT
R521 (209h) Clocking (2)
0
0
0
0
0
TOCLK_DIV [2:0]
0
DBCLK_DIV [2:0]
0
OPCLK_DIV [2:0]
0000h
R528 (210h) AIF1 Rate
0
0
0
0
0
0
0
0
AIF1_SR [3:0]
AIF1CLK_RATE [3:0]
0083h
R529 (211h) AIF2 Rate
0
0
0
0
0
0
0
0
AIF2_SR [3:0]
AIF2CLK_RATE [3:0]
0083h
R530 (212h) Rate Status
0
0
0
0
0
0
0
0
0
0
0
0
SR_ERROR [3:0]
0000h
R544 (220h) FLL1 Control (1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL1_
OSC_E
NA
FLL1_
ENA
0000h
R545 (221h) FLL1 Control (2)
0
0
FLL1_OUTDIV [5:0]
0
0
0
0
0
FLL1_FRATIO [2:0]
0000h
R546 (222h) FLL1 Control (3)
FLL1_K [15:0]
0000h
R547 (223h) FLL1 Control (4)
0
FLL1_N [9:0]
0
0
0
0
0
0000h
R548 (224h) FLL1 Control (5)
0
0
0
FLL1_FRC_NCO_VAL [5:0]
FLL1_
FRC_N
CO
0
FLL1_REFCLK_
DIV [1:0]
0
FLL1_REFCLK_
SRC [1:0]
0C80h
R576 (240h) FLL2 Control (1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL2_
OSC_E
NA
FLL2_
ENA
0000h
R577 (241h) FLL2 Control (2)
0
0
FLL2_OUTDIV [5:0]
0
0
0
0
0
FLL2_FRATIO [2:0]
0000h
R578 (242h) FLL2 Control (3)
FLL2_K [15:0]
0000h
R579 (243h) FLL2 Control (4)
0
FLL2_N [9:0]
0
0
0
0
0
0000h
R580 (244h) FLL2 Control (5)
0
0
0
FLL2_FRC_NCO_VAL [5:0]
FLL2_
FRC_N
CO
0
FLL2_REFCLK_
DIV [1:0]
0
FLL2_REFCLK_
SRC [1:0]
0C80h
R768 (300h) AIF1 Control (1)
AIF1A
DCL_S
RC
AIF1A
DCR_S
RC
AIF1A
DC_TD
M
0
0
0
0
AIF1_B
CLK_I
NV
AIF1_L
RCLK_
INV
AIF1_WL [1:0] AIF1_FMT [1:0]
0
0
0
4050h
R769 (301h) AIF1 Control (2)
AIF1D
ACL_S
RC
AIF1D
ACR_S
RC
0
0
AIF1DAC_BOO
ST [1:0]
0
AIF1_
MONO
0
0
0
AIF1D
AC_C
OMP
AIF1D
AC_C
OMPM
ODE
AIF1A
DC_C
OMP
AIF1A
DC_C
OMPM
ODE
AIF1_L
OOPB
ACK
4000h
R770 (302h) AIF1 Master/Slave
AIF1_T
RI
AIF1_
MSTR
AIF1_C
LK_FR
C
AIF1_L
RCLK_
FRC
0
0
0
0
0
0
0
0
0
0
0
0
0000h
R771 (303h) AIF1 BCLK
0
0
0
0
0
0
0
AIF1_BCLK_DIV [4:0]
0
0
0
0
0040h
R772 (304h) AIF1ADC LRCLK
0
0
0
0
AIF1A
DC_LR
CLK_D
IR
AIF1ADC_RATE [10:0]
0040h
R773 (305h) AIF1DAC LRCLK
0
0
0
0
AIF1D
AC_LR
CLK_D
IR
AIF1DAC_RATE [10:0]
0040h
R774 (306h) AIF1DAC Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1D
ACL_D
AT_IN
V
AIF1D
ACR_D
AT_IN
V
0000h
R775 (307h) AIF1ADC Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1A
DCL_D
AT_IN
V
AIF1A
DCR_
DAT_I
NV
0000h
R784 (310h) AIF2 Control (1)
AIF2A
DCL_S
RC
AIF2A
DCR_S
RC
AIF2A
DC_TD
M
AIF2A
DC_TD
M_CH
AN
0
0
0
AIF2_B
CLK_I
NV
AIF2_L
RCLK_
INV
AIF2_WL [1:0] AIF2_FMT [1:0]
0
0
0
4050h
R785 (311h) AIF2 Control (2)
AIF2D
ACL_S
RC
AIF2D
ACR_S
RC
AIF2D
AC_TD
M
AIF2D
AC_TD
M_CH
AN
AIF2DAC_BOO
ST [1:0]
0
AIF2_
MONO
0
0
0
AIF2D
AC_C
OMP
AIF2D
AC_C
OMPM
ODE
AIF2A
DC_C
OMP
AIF2A
DC_C
OMPM
ODE
AIF2_L
OOPB
ACK
4000h



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