 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
WM8994ECS/R 数据表(PDF) 246 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8994ECS/R 数据表(HTML) 246 Page - Cirrus Logic |
|
|
246 / 363 page  WM8994 246 Rev 4.6 REGISTER MAP The WM8994 control registers are listed below. Note that only the register addresses described here should be accessed; writing to other addresses may result in undefined behaviour. Register bits that are not documented should not be changed from the default values. REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R0 (0h) Software Reset SW_RESET [15:0] 0000h R1 (1h) Power Management (1) 0 0 SPKO UTR_E NA SPKO UTL_E NA HPOU T2_EN A 0 HPOU T1L_E NA HPOU T1R_E NA 0 0 MICB2 _ENA MICB1 _ENA 0 VMID_SEL [1:0] BIAS_ ENA 0000h R2 (2h) Power Management (2) 0 TSHUT _ENA TSHUT _OPDI S 0 OPCLK _ENA 0 MIXINL _ENA MIXIN R_ENA IN2L_E NA IN1L_E NA IN2R_ ENA IN1R_ ENA 0 0 0 0 6000h R3 (3h) Power Management (3) 0 0 LINEO UT1N_ ENA LINEO UT1P_ ENA LINEO UT2N_ ENA LINEO UT2P_ ENA SPKRV OL_EN A SPKLV OL_EN A MIXOU TLVOL _ENA MIXOU TRVOL _ENA MIXOU TL_EN A MIXOU TR_EN A 0 0 0 0 0000h R4 (4h) Power Management (4) 0 0 AIF2A DCL_E NA AIF2A DCR_E NA AIF1A DC2L_ ENA AIF1A DC2R_ ENA AIF1A DC1L_ ENA AIF1A DC1R_ ENA 0 0 DMIC2 L_ENA DMIC2 R_ENA DMIC1 L_ENA DMIC1 R_ENA ADCL_ ENA ADCR_ ENA 0000h R5 (5h) Power Management (5) 0 0 AIF2D ACL_E NA AIF2D ACR_E NA AIF1D AC2L_ ENA AIF1D AC2R_ ENA AIF1D AC1L_ ENA AIF1D AC1R_ ENA 0 0 0 0 DAC2L _ENA DAC2R _ENA DAC1L _ENA DAC1R _ENA 0000h R6 (6h) Power Management (6) 0 0 0 0 0 0 0 0 0 0 AIF3_T RI AIF3_ADCDAT_ SRC [1:0] AIF2_A DCDA T_SRC AIF2_D ACDAT _SRC AIF1_D ACDAT _SRC 0000h R21 (15h) Input Mixer (1) 0 0 0 0 0 0 0 IN1RP _MIXIN R_BO OST IN1LP_ MIXINL _BOO ST INPUT S_CLA MP 0 0 0 0 0 0 0000h R24 (18h) Left Line Input 1&2 Volume 0 0 0 0 0 0 0 IN1_V U IN1L_ MUTE IN1L_Z C 0 IN1L_VOL [4:0] 008Bh R25 (19h) Left Line Input 3&4 Volume 0 0 0 0 0 0 0 IN2_V U IN2L_ MUTE IN2L_Z C 0 IN2L_VOL [4:0] 008Bh R26 (1Ah) Right Line Input 1&2 Volume 0 0 0 0 0 0 0 IN1_V U IN1R_ MUTE IN1R_ ZC 0 IN1R_VOL [4:0] 008Bh R27 (1Bh) Right Line Input 3&4 Volume 0 0 0 0 0 0 0 IN2_V U IN2R_ MUTE IN2R_ ZC 0 IN2R_VOL [4:0] 008Bh R28 (1Ch) Left Output Volume 0 0 0 0 0 0 0 HPOU T1_VU HPOU T1L_Z C HPOU T1L_M UTE_N HPOUT1L_VOL [5:0] 006Dh R29 (1Dh) Right Output Volume 0 0 0 0 0 0 0 HPOU T1_VU HPOU T1R_Z C HPOU T1R_M UTE_N HPOUT1R_VOL [5:0] 006Dh R30 (1Eh) Line Outputs Volume 0 0 0 0 0 0 0 0 0 LINEO UT1N_ MUTE LINEO UT1P_ MUTE LINEO UT1_V OL 0 LINEO UT2N_ MUTE LINEO UT2P_ MUTE LINEO UT2_V OL 0066h R31 (1Fh) HPOUT2 Volume 0 0 0 0 0 0 0 0 0 0 HPOU T2_MU TE HPOU T2_VO L 0 0 0 0 0020h R32 (20h) Left OPGA Volume 0 0 0 0 0 0 0 MIXOU T_VU MIXOU TL_ZC MIXOU TL_MU TE_N MIXOUTL_VOL [5:0] 0079h R33 (21h) Right OPGA Volume 0 0 0 0 0 0 0 MIXOU T_VU MIXOU TR_ZC MIXOU TR_M UTE_N MIXOUTR_VOL [5:0] 0079h R34 (22h) SPKMIXL Attenuation 0 0 0 0 0 0 0 SPKAB _REF_ SEL 0 DAC2L _SPKM IXL_V OL MIXINL _SPKM IXL_V OL IN1LP_ SPKMI XL_VO L MIXOU TL_SP KMIXL _VOL DAC1L _SPKM IXL_V OL SPKMIXL_VOL [1:0] 0003h |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
