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数据搜索系统，热门电子元器件搜索 |
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WM8994ECS/R 数据表(PDF) 244 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 244 Page - Cirrus Logic |
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244 / 363 page  WM8994 244 Rev 4.6 QUICK START-UP AND SHUTDOWN The default control seq uences (see “Control Write Sequencer”) contain only the register writes necessary to enable or disable specific output drivers. It is therefore necessary to configure the signal path and gain settings before commanding any of the default start-up sequences. This section describes minimum control sequences to configure the WM8994 for DAC to Headphone playback. Note that these sequences are provided for guidance only; application software should be verified and tailored to ensure optimum performance. Table 142 describes an example control sequence to enable DAC playback to HPOUT1L and HPOUT1R path. This involves DAC enable, signal path configuration and mute control, together with the default “Headphone Cold Start-Up” sequence. Table 143 describes an example control sequence to disable the direct DAC to Headphone path. REGISTER VALUE DESCRIPTION R5 (0005h) 0003h Enable DAC1L and DAC1R R45 (002Dh) 0100h Enable path from DAC1L to HPOUT1L R46 (002Eh) 0100h Enable path from DAC1R to HPOUT1R R272 (0110h) 8100h Initiate Control Write Sequencer at Index Address 0 (00h) (Headphone Cold Start-Up sequence) Delay 300ms Note: Delay must be inserted in the sequence to allow the Control Write Sequencer to finish. Any control interface writes to the CODEC will be ignored while the Control Write Sequencer is running. R1056 (0420h) 0000h Soft un-mute DAC1L and DAC1R Table 142 DAC to Headphone Direct Start-Up Sequence REGISTER VALUE DESCRIPTION R1056 (0420h) 0200h Soft mute DAC1L and DAC1R R272 (0110h) 812Ah Initiate Control Write Sequencer at Index Address 42 (2Ah) (Generic Shut-Down) Delay 525ms Note: Delay must be inserted in the sequence to allow the Control Write Sequencer to finish. Any control interface writes to the CODEC will be ignored while the Control Write Sequencer is running. R45 (002Dh) 0000h Disable path from DAC1L to HPOUT1L R46 (002Eh) 0000h Disable path from DAC1R to HPOUT1R R5 (0005h) 0000h Disable DAC1L and DAC1R Table 143 DAC to Headphone Direct Shut-Down Sequence In both cases, the WSEQ_BUSY bit (in Register R272, see Table 121) will be set to 1 while the Control Write Sequence runs. When this bit returns to 0, the remaining steps of the sequence may be executed. |
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