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WM8994ECS/R 数据表(PDF) 240 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 240 Page - Cirrus Logic |
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240 / 363 page  WM8994 240 Rev 4.6 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R520 (0208h) Clocking (1) 4 TOCLK_ENA 0 Slow Clock (TOCLK) Enable 0 = Disabled 1 = Enabled This clock is required for zero-cross timeout. 3 AIF1DSPCLK_EN A 0 AIF1 Processing Clock Enable 0 = Disabled 1 = Enabled 2 AIF2DSPCLK_EN A 0 AIF2 Processing Clock Enable 0 = Disabled 1 = Enabled 1 SYSDSPCLK_EN A 0 Digital Mixing Processor Clock Enable 0 = Disabled 1 = Enabled R544 (0220h) FLL1 Control (1) 0 FLL1_ENA 0 FLL1 Enable 0 = Disabled 1 = Enabled This should be set as the final step of the FLL1 enable sequence, ie. after the other FLL registers have been configured. R576 (0240h) FLL2 Control (1) 0 FLL2_ENA 0 FLL2 Enable 0 = Disabled 1 = Enabled This should be set as the final step of the FLL2 enable sequence, ie. after the other FLL registers have been configured. Table 138 Power Management |
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