WM8994ECSSLASHR datasheet(242/363 Pages) CIRRUS

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WM8994

242

Rev 4.6

DCVDD

AVDD2

Vpora

Vpord_off

Internal POR

Device ready

Vpora_on

POR active

POR undefined

Figure 86 Power On Reset Timing - DCVDD enabled/disabled first

The POR

¯¯¯ signal is undefined until AVDD2 has exceeded the minimum threshold, Vpora. Once this

threshold has been exceeded, POR

¯¯¯ is asserted low and the chip is held in reset. In this condition, all

writes to the control interface are ignored. Once AVDD2 and DCVDD have reached their respective

power on thresholds, POR

¯¯¯ is released high, all registers are in their default state, and writes to the

control interface may take place.

Note that a power-on reset period, TPOR, applies after AVDD2 and DCVDD have reached their

respective power on thresholds. This specification is guaranteed by design rather than test.

On power down, POR

¯¯¯ is asserted low when either AVDD2 or DCVDD falls below their respective

power-down thresholds.

Typical Power-On Reset parameters for the WM8994 are defined in Table 140.

SYMBOL

DESCRIPTION

TYP

UNIT

Vpora_on

Power-On threshold (AVDD2)

1.15

Vpora_off

Power-Off threshold (AVDD2)

1.14

Vpord_on

Power-On threshold (DCVDD)

0.56

Vpord_off

Power-Off threshold (DCVDD)

0.55

TPOR

Minimum Power-On Reset period

100

Table 140 Typical Power-On Reset Parameters

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