STDRIVE102HTR datasheet(24/56 Pages) STMICROELECTRONICS

24 / 56 page

When INx is toggled, the logic changes the state of both the high-side x and the low-side x with a specific

sequence: the driver that is currently HIGH is set LOW; then, after a deadtime, the complementary driver is set

HIGH.

The deadtime is necessary to avoid dangerous cross-conductions. The deadtime is managed by the internal logic,

according to the device’s setting. Since the time required to completely discharge the gate of the external

MOSFET is tcc,off, it is also equivalent to the deadtime (Figure 14).

Figure 14. Current management using EN/IN mode

-Ihold,off

-Iclamp

tcc,off

tcc,on

INx

ENx

VGS,LSx

VGS,HSx

+Ihold,on

+IGATE,on

-IGATE,off

hold

off

gate

hold

gate

off

clamp

hold

off

-Ihold,off

-Iclamp

+Ihold,on

+IGATE,on

-IGATE,off

tcc,off

tcc,on

gate

hold

off

clamp

gate

off

Current

capability

Current

capability

hold

The current and the timing of the driver are strictly related: they must be configured by the user through the TCC

and IGATE pins, according to the external power MOSFET and the slew rate required by the application.

The IGATE level must be chosen according to Table 9 and considering the gate-drain charge Qgd of the driven

MOSFET and the rising time/fall time and thus the slew rate of the OUTx pin of the half-bridge.

Equation 1

IGATE,on/off≅Qgdtsw

(1)

The current to be considered, whether IGATE,on or IGATE,off depends on which MOSFET of the half-bridge is hard-

switching. Eq. (1) provides an indication to select a suitable driving current for the application; however, it must be

considered that Cgd varies with the VDS of the MOSFET, therefore some margins must be taken.

The tsw in Eq. (1) represents the switching time of the half-bridge OUTx and it is strictly related to the slew rate.

Equation 2

SROUTx≅VMtsw

(2)

STDRIVE102BH, STDRIVE102H

Device description

DS14545 - Rev 1

page 24/56

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