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STR910FAM32 数据表(PDF) 85 Page - STMicroelectronics |
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STR910FAM32 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 99 page ![]() STR91xFAx32 STR91xFAx42 STR91xFAx44 Electrical characteristics 85/99 7.12.5 SPI electrical characteristics VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified. Figure 29. SPI slave timing diagram with CPHA=0 Table 45. SPI electrical characteristics Symbol Parameter Test Conditions Value Unit Typ Max fSCLK 1/tc(SCLK) SPI clock frequency Master 24 MHz Slave 4 tr(SCLK) SPI clock rise and fall times 50pF load 0.1 V/ns tf(SCLK) tsu(SS) SS setup time Slave 1 tPCLK th(SS) SS hold time Slave 1 tw(SCLKH) tw(SCLKL) SCLK high and low time Master Slave 1 tsu(MI) tsu(SI) Data input setup time Master Slave 5 th(MI) th(SI) Data input hold time Master Slave 6 ta(SO) Data output access time Slave 6 tdis(SO) Data output disable time Slave 6 tv(SO) Data output valid time Slave (after enable edge) 6 th(SO) Data output hold time 0 tv(MO) Data output valid time Master (before capture edge) 0.25 th(MO) Data output hold time 0.25 NSS INPUT CPHA=0 MOSI INPUT MISO OUTPUT CPHA=0 tc(SCLK) tw(SCLKH) tw(SCLKL) tr(SCLK) tf(SCLK) tv(SO) ta(SO) tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 tsu(NSS) th(NSS) tdis(SO) th(SO) BIT1 IN |
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