PM6641 datasheet(20/47 Pages) STMICROELECTRONICS

20 / 47 page

Device description

PM6641

20/47

7.1

Memory supply

The DDR2/3 section of PM6641 is based on the VDDQ rail, the VTT termination rail and the

VTTREF reference voltage buffer.

The VDDQ rail is provided by a step-down switching regulator whose output voltage, by

default, is set to 1.8 V, in order to be compliant with DDR2 JEDEC specs. The output voltage

can also be adjusted using an external resistor divider. This rail performs latched Output

Under-Voltage and Over-Voltage and auto-recovery Current Limit, without requiring external

sensing resistor.

The VTT termination rail is supplied by a Low Drop-Out (LDO) Linear Regulator, able to sink

and source up to 2 A peak current. This regulator follows the half of the VDDQ rail and is a

replica of the VTTREF reference voltage buffer. When LDOIN is directly supplied by VDDQ,

i.e. the PM6641 1S8 rail, VTT and VDDQ can perform the so called Tracking Discharge, in

compliance with the JEDEC specs, as described in the following section. If higher efficiency

is required, VTT can be supplied by a lower voltage rail. An output capacitor of at least 20 µF

is the only external component required.

The VTTREF reference voltage buffer is always in tracking with the half of VDDQ and is able

to sink and source up to 15mA with an accuracy of ±2 % relative to VDDQ half. A 10 nF up

to 100nF bypass capacitor for stability purposes is required.

7.1.1

VDDQ switching regulator

The VDDQ rail is provided by a constant frequency current-mode buck regulator, whose

frequency is set by inserting an external resistor between SET_SWF pin and AGND (see

Chapter 7.8: Switching frequency selection on page 29 section for details). The output

voltage can easily be set to 1.8 V by connecting the feedback pin VFB_1S8 directly to the

output rail, avoiding the use of external components. However, if a different output voltage is

desired, the VFB_1S8 pin must be connected to the central tap of a resistor divider.

The output voltage can be adjusted from 0.8V up to the input voltage value, decreased by a

drop due to the high-side MOSFET on resistance.

(see Chapter 7.5: Output voltage divider on page 27 section for details).

The control loop needs to be compensated by inserting a resistor-capacitor series

connected between the COMP_1S8 pin and ground; if electrolytic capacitor with relevant

equivalent series resistance (ESR) are used, an additional capacitor between the

COMP_1S8 pin and ground can be useful (see Chapter 7.3: SW regulators control loop on

page 24 section for details). The classical slope compensation is internally implemented

and no external components are required.

The internal High-Side PMOS and Low-Side NMOS allow the regulator to source an

average current of 2.8 A and a peak current of 5 A. The peak current limit protection is

performed by sensing the internal high side MOSFET current and can be decreased by

inserting an external resistor between CSNS pin and AGND (see Chapter 7.10: Peak

current limit on page 31 section for details).

This 1S8 rail is able to protect the load from Over-Voltage and Under-Voltage protection,

which avoid the output to be higher than 120 % or lower than 60 % of the nominal value (see

Chapter 7.11.1: Output over voltage on page 33 and Chapter 7.11.2: Output under voltage

on page 33 section for details).

When the EN_1S8 pin goes high the VDDQ rail is turned on and the output voltage soft-start

is performed by slowly charging the rail output capacitor; this behavior is achieved because

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