PM6641 datasheet(22/47 Pages) STMICROELECTRONICS

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Device description

PM6641

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7.1.4

S3 and S5 power management pins

According to DDR2/3 memories supply requirements, the PM6641 can manage all S0 to S5

system states just connecting EN_VTT – EN_1S8 pins to their respective sleep-mode

signals in the notebook’s motherboard: connect EN_1S8 to S5 and EN_VTT to S3.

Keeping EN_VTT and EN_1S8 high, the S0 (Full-On) state is decoded and the outputs are

alive.

In S3 state (EN_1S8=1, EN_VTT =0), the PM6641 maintains VDDQ and VTTREF outputs

active and VTT output in high-impedance as needed.

In S4/S5 states (EN_1S8= EN_VTT =0) all outputs are turned off and, according to DSCG

pin voltage, the proper Soft-End is performed (see Chapter 7.7: Outputs Soft-End on

page 29 section for details).

The following table resumes the DDR power supply states.

7.2

Chipset supply

The chipset power supply section is based on two constant frequency current-mode buck

regulators with a pre-fixed output voltage of 1.5 V and 1.05 V.

These two independent rails have programmable switching frequency, set by inserting an

external resistor between SET_SWF pin and AGND. The PM6641 allows also to manage

the switching regulators phases for 1.5V, 1.05V and 1.8V (VDDQ) rails in order to limit the

RMS input current (see Chapter 7.8: Switching frequency selection on page 29 and

Chapter 7.9: Phase management on page 30 section for details).

The output voltages can easily be set to the pre-fixed value by connecting the feedback pins

VFB_1S5 and VFB_1S05 directly to the respective output rail, avoiding the use of external

components. However, if a different output voltage is desired, the feedback pins can be

independently connected to the central tap of a resistor divider.

The output voltage can be adjusted from 0.8V up to the input voltage value, decreased by a

drop due to the high-side MOSFET on resistance.

(see Chapter 7.5: Output voltage divider on page 27 section for details).

Both regulators are current-mode step-down switching regulators whose control loop needs

to be compensated by inserting a resistor-capacitor series connected between the

compensation pin (COMP_1S5 and COMP_1S05) and ground; if electrolytic capacitor with

relevant equivalent series resistance (ESR) are used, an additional capacitor between this

compensation pin and ground can be useful (see Chapter 7.3: SW regulators control loop

on page 24 section for details). The classical slope compensation, which allows the peak

current mode loop to avoid sub-harmonic instability with duty cycle greater than 50%, is

internally implemented and no further external components are required.

Table 8. S3 and S5 sleep-states decoding

S3 (EN_VTT) S5 (EN_1S8)

System state

VDDQ

VTTREF

VTT

(Full-On)

(Suspend-To-RAM)

Hi-Z

S4/S5

(Suspend-To-Disk)

Off (Discharge) Off (Discharge) Off (Discharge)

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