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FDMS8672AS 数据表(PDF) 2 Page - Texas Instruments |
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FDMS8672AS 数据表(HTML) 2 Page - Texas Instruments |
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2 / 43 page ![]() XCON VBST1 DRVH1 SW1 DRVL1 GND VREG5 VREG5 GND Control Logic PGOOD1 GND Delay + + + + 1V+5%/10% 1V-5%/10% 1V-30% 1V+15% + PWM Skip Ramp Comp + + VFB1 COMP1 EN1 Enable/ Soft-start 1V + CSN1 CSP1 Discharge Control GND 100mV + V5SW 4.7V/4.5V GND VREG5 + VREF2 GND GND 1.25V GND 1.25V GND + VREG3 + 4.7V/4.5V VIN EN + 4.2V/3.8V 150/140 Deg-C V5OK THOK Ready + SKIPSEL1 IMON1 OSC RF CLK1 CLK2 Fault1 SDN1 UVP OVP Fault2 SDN2 Ready GND Channel-1Switchershown + VREF2 CLK1 VREF2 + OCP Ramp Comp + N-OCP 100mV OOA Ctrl + VFB-AMP CS-AMP Amp. Filter EN1OK V5SWOK Clamp(+) Clamp(-) AZC TPS51222 SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS51222 |
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