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FDMS8672AS 数据表(PDF) 7 Page - Texas Instruments |
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FDMS8672AS 数据表(HTML) 7 Page - Texas Instruments |
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7 / 43 page ![]() DEVICE INFORMATION PINOUT DRVH2 VIN VREG3 EN2 DRVH1 V5SW RF EN1 PGOOD2 SKIPSEL2 CSP2 CSN2 PGOOD1 SKIPSEL1 CSP1 CSN1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 TPS51122 RTVPACKAGE (TOP VIEW) TPS51222 www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. COMP1 10 Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin I to VREF2 for proper loop compensation with current mode operation. COMP2 15 CSN1 8 Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the I current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal. CSN2 17 CSP1 7 Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should I/O be used to extract voltage drop across DCR. 0.1- µF is a good value to start the design. See the current CSP2 18 sensing scheme section for more details. DRVH1 1 High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive O voltage corresponds to VBST to SW voltage. DRVH2 24 DRVL1 30 O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, and GND referenced driver. DRVL2 27 VREF2 and VREG5 linear regulators enable pin. When turning on, apply greater than 1.2 V and less than 6 EN 12 I V. Connect to GND to disable. EN1 4 Channel 1 and channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55 V and less than 6 V. I Connect to GND to disable. Adjustable soft-start capacitance to be attached here. EN2 21 GND 28 – Ground IMON1 11 O Current monitor outputs for channel 1 and channel 2. Adding an RC filter is recommended. IMON2 14 PGOOD1 5 Powergood window comparator outputs for channel 1 and channel 2. The recommended applied voltage O should be less than 6 V, and the recommended pull-up resistance value is from 100 k Ω to 1 MΩ. PGOOD2 20 Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for RF 3 I/O synchronization. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s) :TPS51222 |
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