5.0-V, 100-mA LDO (VREG5)

VREG5 SWITCHOVER

BASIC PWM OPERATIONS

TPS51222

SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

A 5.0-V, 100-mA, linear regulator is integrated in the TPS51222. This LDO services the main analog supply rail

and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-

µF (at least

4.7-

µF), high-quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the device.

When EN1 is high, PGOOD1 indicates GOOD and a voltage of more than 4.8 V is applied to V5SW, the internal

5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after an 7.7-ms delay. When the

V5SW voltage becomes lower than 4.65 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is

turned off, and the internal 5V-LDO resumes immediately.

The main control loop of the SMPS is designed as a fixed frequency, peak current mode, pulse width modulation

(PWM) controller. It achieves stable operation with any type of output capacitors, including low ESR capacitor(s)

such as ceramic or specialty polymer capacitors.

The current mode scheme uses the output voltage information and the inductor current information to regulate

the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the

internal 1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The

inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another

transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If

the output voltage decreases, the TPS51222 increases the target inductor current to raise the output voltage.

Alternatively, if the output voltage rises, the TPS51222 decreases the target inductor current to reduce the output

voltage.

At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side

MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is

determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp

compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The

high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the

controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each

OFF state to keep the conduction loss minimum.

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