7.10 Current Wake Comparator (continued)

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

tWAKE(SU)

Wake up comparator

startup time

[WKCHGEN] = 0 and [WKDSGEN] = 0 to

[WKCHGEN] = 1 and [WKDSGEN] = 1

250

640

µs

7.11 Coulomb Counter

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

Input voltage range

–100

100

mV

Full scale range

–VREF1/10

+VREF1/10

mV

Differential nonlinearity

16-bit, no missing codes

±1

LSB

Integral nonlinearity

16-bit, best fit over input voltage range

±5.2

±22.3

LSB

Offset error

16-bit, post-calibration

±1.3

±2.6

LSB

Offset error drift

15-bit + sign, post-calibration

0.04

0.07 LSB/°C

Gain error

15-bit + sign, over input voltage range

±131

±492

LSB

Gain error drift

15-bit + sign, over input voltage range

4.3

9.8 LSB/°C

Effective input resistance

2.5

MΩ

7.12 ADC Digital Filter

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

tCONV

ADCTL[SPEED1, SPEED0] = 0, 0

31.25

ms

ADCTL[SPEED1, SPEED0] = 0, 1

15.63

ADCTL[SPEED1, SPEED0] = 1, 0

7.81

ADCTL[SPEED1, SPEED0] = 1, 1

1.95

Resolution

No missing codes, ADCTL[SPEED1, SPEED0] =

0, 0

16

Bits

Effective resolution

With sign, ADCTL[SPEED1, SPEED0] = 0, 0

14

15

Bits

With sign, ADCTL[SPEED1, SPEED0] = 0, 1

13

14

With sign, ADCTL[SPEED1, SPEED0] = 1, 0

11

12

With sign, ADCTL[SPEED1, SPEED0] = 1, 1

9

10

7.13 ADC Multiplexer

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

K

Scaling factor

VC1–VSS, VC2–VC1

0.1980

0.2000

0.2020

—

VC2–VSS, PACK–VSS

0.0485

0.050

0.051

VREF1/2

0.490

0.500

0.510

VIN

Input voltage range

VC2–VSS, PACK–VSS

–0.2

20

V

TS1

–0.2

0.8 × VREF1

TS1

–0.2

0.8 × VREG

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BQ28Z610-R1

SLUSE07B – JANUARY 2020 – REVISED JANUARY 2022

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