7.24 Current Protection Timing

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

NOM

MAX

UNIT

tOCD

OCD detection delay

time

1

31

ms

ΔtOCD

OCD detection delay

time program step

2

ms

tSCC

SCC detection delay

time

0

915

µs

ΔtSCC

SCC detection delay

time program step

61

µs

tSCD1

SCD1 detection delay

time

PROTECTION_CONTROL[SCDDx2] = 0

0

915

µs

PROTECTION_CONTROL[SCDDx2] = 1

0

1850

ΔtSCD1

SCD1 detection delay

time program step

PROTECTION_CONTROL[SCDDx2] = 0

61

µs

PROTECTION_CONTROL[SCDDx2] = 1

121

tSCD2

SCD2 detection delay

time

PROTECTION_CONTROL[SCDDx2] = 0

0

458

µs

PROTECTION_CONTROL[SCDDx2] = 1

0

915

ΔtSCD2

SCD2 detection delay

time program step

PROTECTION_CONTROL[SCDDx2] = 0

30.5

µs

PROTECTION_CONTROL[SCDDx2] = 1

61

tDETECT

Current fault detect time

VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2,

VSRP – VSRN = VT + 3 mV for SCC

160

µs

tACC

Current fault delay time

accuracy

Max delay setting

–10%

10%

7.25 N-CH FET Drive (CHG, DSG)

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

Output voltage ratio

RatioDSG = (VDSG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10

MΩ between PACK and DSG

2.133

2.333

2.467

—

RatioCHG = (VCHG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10

MΩ between BAT and CHG

2.133

2.333

2.467

V(FETON)

Output voltage,

CHG and DSG on

VDSG(ON) = VDSG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ

between PACK and DSG

8.75

9.5

10.25

V

VCHG(ON) = VCHG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ

between VC2 and CHG

8.75

9.5

10.25

V(FETOFF)

Output voltage,

CHG and DSG off

VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and

DSG

–0.4

0.4

V

VCHG(OFF) = VCHG – VBAT, 10 MΩ between VC2 and CHG

–0.4

0.4

tR

Rise time

VDSG from 0% to 35% VDSG (ON)(TYP), VBAT ≥ 2.2 V, CL =

4.7 nF between DSG and PACK, 5.1 kΩ between DSG

and CL, 10 MΩ between PACK and DSG

200

500

µs

VCHG from 0% to 35% VCHG (ON)(TYP), VVC2 ≥ 2.2 V, CL =

4.7 nF between CHG and VC2, 5.1 kΩ between CHG and

CL, 10 MΩ between VC2 and CHG

200

500

tF

Fall time

VDSG from VDSG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF

between DSG and PACK, 5.1 kΩ between DSG and CL,

10 MΩ between PACK and DSG

40

300

µs

VCHG from VCHG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF

between CHG and VC2, 5.1 kΩ between CHG and CL, 10

MΩ between VC2 and CHG

40

200

www.ti.com

BQ28Z610-R1

SLUSE07B – JANUARY 2020 – REVISED JANUARY 2022

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

11

Product Folder Links: BQ28Z610-R1