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CDCLVC1102 数据表(PDF) 5 Page - Texas Instruments |
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CDCLVC1102 数据表(HTML) 5 Page - Texas Instruments |
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5 / 37 page ![]() 5 CDCLVC1102, CDCLVC1103, CDCLVC1104 CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112 www.ti.com SCAS895B – MAY 2010 – REVISED FEBRUARY 2017 Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110 CDCLVC1112 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This value is limited to 4.6 V maximum. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Supply voltage –0.5 4.6 V VIN Input voltage(2) –0.5 VDD + 0.5 V VO Output voltage(2) –0.5 VDD + 0.5 V IIN Input current –20 20 mA IO Continuous output current –50 50 mA TJ Maximum junction temperature 125 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 3.3-V supply 3.0 3.3 3.6 V 2.5-V supply 2.3 2.5 2.7 VIL Low-level input voltage VDD = 3.0 V to 3.6 V VDD/2 – 600 mV VDD = 2.3 V to 2.7 V VDD/2 – 400 VIH High-level input voltage VDD = 3.0 V to 3.6 V VDD/2 + 600 mV VDD = 2.3 V to 2.7 V VDD/2 + 400 Vth Input threshold voltage VDD = 2.3 V to 3.6 V VDD/2 mV tr / tf Input slew rate 1 4 V/ns tw Minimum pulse width at CLKIN VDD = 3.0 V to 3.6 V 1.8 ns VDD = 2.3 V to 2.7 V 2.75 fCLK LVCMOS clock Input Frequency VDD = 3.0 V to 3.6 V DC 250 MHz VDD = 2.3 V to 2.7 V DC 180 TA Operating free-air temperature –40 85 °C |
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