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CDCLVC1102, CDCLVC1103, CDCLVC1104

CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112

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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017

Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110

CDCLVC1112

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Copyright © 2010–2017, Texas Instruments Incorporated

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVC11xx family is a low additive jitter LVCMOS buffer solution that can operate up to 250 MHz at and

180 MHz at VDD = 2.5 V. Low output skew as well as the ability for asynchronous output enable is featured to

simultaneously enable or disable buffered clock outputs as necessary in the application.

9.2 Typical Application

Figure 10. Example System Configuration

9.2.1 Design Requirements

The CDCLVC11xx shown in Figure 10 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator.

The CPU is configured to control the output state through 1G.

The configuration example is driving three LVCMOS receivers in a backplane application with the following

properties:

•

The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the

CDCLVC11xx to closely match the characteristic impedance of the trace to minimize reflections.

•

The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the CDCLVC11xx.

•

The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.

The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is

mismatched.

9.2.2 Detailed Design Procedure

Refer to Figure 5 and the Electrical Characteristics table to determine the appropriate series resistance needed

for matching the output impedance of the CDCLVC11xx to that of the characteristic impedance of the

transmission line.

Unused outputs can be left floating. See the Power Supply Recommendations section for recommended filtering

techniques.