CDCLVC

1112

1

1G

2

GND

3

CLKIN

4

5

6

7

8

9

10

16

17

18

19

20

21

22

23

24

Y 1

Y 2

VDD

VDD

Y 3

Y4

VDD

GND

Y0

Y11

Y 5

GND

Y6

Y 7

Y9

VDD

Y 8

GND

11

12

13

14

15

GND

Y 10

VDD

CDCLVC

1106

CDCLVC

1110

CDCLVC

1102

CDCLVC

1103

CDCLVC

1104

CDCLVC

1108

Y0

Y1

Y2

Y3

Yn

CLKIN

LV

CMOS

1G

LV

CMOS

LV

CMOS

LV

CMOS

LV

CMOS

LV

CMOS

•

•

•

10

CDCLVC1102, CDCLVC1103, CDCLVC1104

CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112

SCAS895B – MAY 2010 – REVISED FEBRUARY 2017

www.ti.com

Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110

CDCLVC1112

Submit Documentation Feedback

Copyright © 2010–2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The CDCLVC11xx family of devices is a low-jitter and low-skew LVCMOS fan-out buffer solution. For best signal

integrity, it is important to match the characteristic impedance of the CDCLVC11xx's output driver with that of the

transmission line. Figure 5 and Figure 6 show the proper configuration per configuration for both VDD = 3.3 V and

VDD = 2.5 V. TI recommends placing the series resistor close to the driver to minimize signal reflection.

8.2 Functional Block Diagram

Table 1. Output Logic Table

INPUTS

OUTPUTS

CLKIN

1G

Yn

X

L

L

L

H

L

H

H

H

8.3 Feature Description

The outputs of the CDCLVC11xx can be disabled by driving the asynchronous output enable pin (1G) low.

Unused output can be left floating to reduce overall system component cost. All supply and ground pins must be

connected to VDD and GND, respectively.

8.4 Device Functional Modes

The CDCLVC11xx operates from supplies between 2.5 V and 3.3 V.