fO − Output Frequency − MHz

−250

−200

−150

−100

−50

0

50

100

150

200

250

0

25

50

75

100 125 150 175 200 225 250

IF

G018

IF + fDAC/4

IF − fDAC/4

IF − fDAC/2

IF − fDAC y 3/4

fO − Output Frequency − MHz

0

50

100

150

200

250

0

25

50

75

100 125 150 175 200 225 250

G019

IF − fDAC y 3/4

IF − fDAC/4

IF + fDAC/4

IF − fDAC/2

IF

DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

Figure 28(b) shows the location of the largest spurious signals for fDAC = 500 MSPS and 4× interpolation for a

real output signal. With a real output signal, there is no distinction between negative and positive frequencies,

and therefore the signals that appear at negative frequencies with a complex signal potentially fall near the

wanted signal. In particular, at IFs near fDAC/8, fDAC/4, and fDAC × 3/4 (62.5 MHz, 125 MHz and 187.5 MHz in this

example) the mixing effect results in spurious signals falling near the wanted signal, which may present a

problem depending on the system application. For a frequency-symmetric signal (such as a single WCDMA or

CDMA carrier), operating at exactly fDAC/8, fDAC/4 and fDAC × 3/4, the spurious signal falls completely inside the

wanted signal, which produces a clean spectrum but may result in degradation of the signal quality.

(a)

(b)

Figure 28. Spurious Frequency vs IF

The offset between wanted and spurious signals is maximized at low IFs (< fDAC/8) and at fDAC × 3/16, fDAC ×

5/16 and fDAC × 7/16. For example, with fDATA = 122.88 MSPS and 4× interpolation, operating with IF = fDAC ×

5/16 = 153.6 MHz results in spurious signals at offsets of 60 MHz from the wanted signal.

Figure 29(a) shows the amplitude of each spurious signal as a function of IF in external-clock mode (CLK2

input). The dominant spurious signal is IF – fDAC/2. The amplitudes of the IF + fDAC/4 and IF – fDAC/4 are the

next-highest spurious signals and are approximately at the same amplitude. Finally, at IF frequencies greater

than 100 MHz, small spurious signals at IF fDAC/8 and IF – fDAC × 3/4 are measurable.

Figure 29(b) shows the amplitude of each spurious signal as a function of IF in PLL clock mode (CLK1 input).

Generating the DAC clock with the onboard PLL/VCO increases the IF – fDAC/2 by 10 dB and the amplitude of

the IF fDAC/4 and IF – fDAC × 3/4 by 25 dB compared to the external-clock mode. The IF fDAC/8 spurs are the

same as in the external-clock mode.

28

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