DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

sel[1:0]: Controls the selection of interpolating filters used; summarized in Table 8.

Table 8. DAC5686 Filter Configuration

sel[1:0]

INTERP. FIR SETTING

00

×2

01

×4

10

×8

11

×16

counter: When asserted, the DAC5686 goes into counter mode and uses an internal counter as a ramp input to

the DAC. The count range is determined by the A-side input data DA[2:0], as summarized in Table 9.

Table 9. DAC5686 Counter Mode Count Range

DA[2:0]

COUNT RANGE

000

All bits D[15:0]

001

Lower 7 bits D[6:0]

010

Mid 4 bits D[10:7]

100

Upper 5 bits D[15:11]

full_bypass: When asserted, the interpolation filters and mixer logic are bypassed, and the data inputs DA[15:0]

and DB[15:0] go straight to the DAC inputs.

Register Name: config_msb

MSB

LSB

ssb

interl

sinc

dith

sync_phstr

nco

sif4

twos

0

0

0

0

0

0

0

0

ssb: In single-sideband mode, assertion inverts the B data; in quadrature modulation mode, assertion routes the

A data path to DACB instead of the B data path.

interl: When asserted, data input to the DAC5686 on channel DA[15:0] is interpreted as a single interleaved

stream (I/Q); channel DB[15:0] is unused.

sinc: Assertion enables the INVSINC filter.

dith: Assertion enables dithering in the PLL.

sync_phstr: Assertion enables the PHSTR input as a sync input to the clock dividers in external single-clock

mode.

nco: Assertion enables the NCO.

sif4: When asserted, the sif interface becomes a 4-pin interface instead of a 3-pin interface. The SDIO pin

becomes an input only, and the SDO is the output.

twos: When asserted, the chip interprets the input data as 2s complement form instead of binary offset.

Register Name: config_usb

MSB

LSB

dualclk

DDS_gain[1:0]

rspect

qflag

pll_rng[1:0]

rev_bbus

0

0

0

0

0

0

0

0

dual_clk: When asserted, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock and

CLK2/CLK2C is the DAC output clock. These two clocks must be phase-aligned within 500 ps to function

properly. When deasserted, CLK2/CLK2C is the DAC output clock and is divided down to generate the input data

clock, which is output on PLLLOCK. Dual clock mode is only available when PLLVDD = 0.

DDS_gain[1:0]: Controls the gain of the DDS so that the overall gain of the DDS is unity. It is important to

40

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