DAC5686

www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

ensure that max(abs(cos(

ωt) + sin(ωt))) < 1. At different frequencies, the summation produces different maximum

outputs and must be reduced. The simplest is fDAC/4 mode where the maximum is 1 and the gain multiply should

be 1 to maintain unity. However, due to the fact that the digital logic does a divide-by-two in this summation, the

gain necessary to achieve unity must be double (DDS_gain[1:0] = 01). Table 10 shows the digital gain necessary

and the actual signal gain needed to make the above equation have a maximum value of 1.

Table 10. Digital Gain for DDS

DDS_gain [1:0]

DIGITAL GAIN

SIGNAL GAIN FOR UNITY

00

1.40625

0.703125

01

2

1

10

1.59375

0.7936

11

1.40625

0.703125

rspect: When asserted, the sin term is negated before being used in mixing. This gives the reverse spectrum in

single-sideband mode.

qflag: When asserted, the QFLAG pin is used by the user as an input indicator during interleaved data input

mode to identify the Q sample. When deasserted, the TxENABLE pin transition is used to start an internal

toggling signal, which is used to interpret the interleaved data sequence; the first sample clocked into the

DAC5686 after TxENABLE goes high is routed through the A data path.

PLL_rng[1:0]: Increases the PLL VCO VtoI current, summarized in Table 11. See Figure 17 for the effect on

VCO gain and range.

Table 11. PLL VCO Vtol Current Increase

PLL_rng[1:0]

VtoI CURRENT INCREASE

00

nominal

01

15%

10

30%

11

45%

rev_bbus[1:0]: When asserted, pin 92 changes from DB15 to DB0, pin 91 changes from DB14 to DB1, etc.,

reversing the order of the DB[15:0] pins.

Register Name: daca_offset_lsb (2s complement)

MSB

LSB

daca_offset[7:0]

0

0

0

0

0

0

0

0

daca_offset[7:0]: The lower 8 bits of the DACA offset

Register Name: daca_gain_lsb (2s complement)

MSB

LSB

daca_gain[7:0]

0

0

0

0

0

0

0

0

daca_gain[7:0]: The lower 8 bits of the DACA gain control register. These lower 8 bits are for fine gain control.

This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%

range.

Register Name: daca_offset_gain_msb (2s complement)

MSB

LSB

daca_offset[10:8]

sleepa

daca_gain[11:8]

0

0

0

0

0

0

0

0

daca_offset[10:8]: The upper 3 bits of the DACA _offset

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