f − Frequency − MHz

−80

−70

−60

−50

−40

−30

−20

−10

0

0

25

50

75

100 125 150 175 200 225 250

G022

IF − fDAC/4

IF − fDAC/2

IF + fDAC/4

Dual-Bus Mode

IOUTB1

IOUTB2

IOUTA1

IOUTA2

16-Bit

DAC

DA[15:0]

DB[15:0]

2fDATA

2y–16y fDATA

fDATA

y2

16-Bit

DAC

2fDATA

y2

FIR1

Edge Triggered

Input Latches

• ••

• ••

DEMUX

B0025-01

DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

Figure 30 shows the DAC5686 output spectrum for the preceding example. The amplitudes of the clock-related

spurs agree quite well with the predicted amplitudes in Table 4.

Figure 30. DAC5686 Output Spectrum With fDAC = 500 MSPS, 4× Interpolation, IF = 85 MHz, and

External-Clock Mode

In dual-bus mode, two separate parallel data streams (I and Q) are input to the DAC5686 on data bus DA and

data bus DB. Dual-bus mode is selected by setting INTERL to 0 in the config_msb register. Figure 31 shows

the DAC5686 data path in dual-bus mode. The dual-bus mode timing diagram is shown in Figure 32 for the PLL

clock mode and in Figure 33 for the external clock mode.

Figure 31. Dual-Bus Mode Data Path

30

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