RT

200

Ω

CLK

1:4

CLKC

Termination Resistor

Swing Limitation

Optional, May Be Bypassed

for Sine Wave Input

CAC

0.1

µF

S0029-01

Ropt

22

Ω

CLK

1:1

CLKC

Optional, Reduces

Clock Feedthrough

CAC

0.01

µF

TTL/CMOS

Source

Ropt

22

Ω

CLK

CLKC

Node CLKC Internally Biased

to CLKVDD 2

TTL/CMOS

Source

0.01

µF

S0030-01

RT

130

Ω

CAC

0.1

µF

CAC

0.1

µF

RT

130

Ω

VTT

Differential

ECL

or

(LV)PECL

Source

+

–

CLK

CLKC

RT

82.5

Ω

RT

82.5

Ω

100

Ω

S0031-01

DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

Figure 47. Preferred Clock Input Configuration

Figure 48. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source

Figure 49. Driving the DAC5686 With a Differential ECL/PECL Clock Source

44

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